From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH] ARM: perf: Don't sleep while atomic when enabling per-cpu interrupts Date: Wed, 10 Sep 2014 19:21:37 +0100 Message-ID: <20140910182137.GL1710@arm.com> References: <1410200814-25878-1-git-send-email-sboyd@codeaurora.org> <20140909113943.GG1754@arm.com> <540F3EE5.90500@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:36454 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751044AbaIJSWL (ORCPT ); Wed, 10 Sep 2014 14:22:11 -0400 Content-Disposition: inline In-Reply-To: <540F3EE5.90500@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Stephen Boyd Cc: "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Rob Clark On Tue, Sep 09, 2014 at 06:54:45PM +0100, Stephen Boyd wrote: > On 09/09/14 04:39, Will Deacon wrote: > > It's interesting that arm64 isn't affected by this problem, since we don't > > update the active_irqs mask for PPIs there and consequently just pass the > > irq instead of the cpu_pmu. I can't see why we actually need to update the > > active_irqs mask for arch/arm/, so could we remove that and follow arm64's > > lead instead? That would remove the need for a new struct definition too. > > > > I guess you're saying that we don't need the active_irqs mask in the > percpu irq case? It looks like we still use it to determine when the > last CPU PMU has been disabled in the non-percpu case. Correct. > Here's the interdiff. Is there a reason arm64 casts data to an unsigned > int pointer when what's passed is an int pointer? There has to be a cast to something because data is a void *. enable_percpu_irq takes an unsigned int, so I guess that's why it was chosen. I'm not fussed either way. Feel free to submit the full patch with my ack: Acked-by: Will Deacon Will