From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH] clk: qcom: fix RCG M/N counter configuration Date: Thu, 19 Mar 2015 22:28:07 -0700 Message-ID: <20150320052807.GA11451@codeaurora.org> References: <1425462575-11486-1-git-send-email-architt@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1425462575-11486-1-git-send-email-architt@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Archit Taneja Cc: mturquette@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org On 03/04, Archit Taneja wrote: > Currently, a RCG's M/N counter (used for fraction division) is set to either > 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether > the corresponding rcg struct has a mnd field specified and a non-zero N. > > In the case where M and N are the same value, the M/N counter is still enabled > by code even though no division takes place. Leaving the RCG in such a state > can result in improper behavior. This was observed with the DSI pixel clock RCG > when M and N were both set to 1. > > Add an additional check (M != N) to enable the M/N counter only when it's needed > for fraction division. > > Signed-off-by: Archit Taneja > --- I'm going to queue this up for 4.1 given that this isn't a new regression. But I'll tag it for stable so that we get it into all the stable trees. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project