From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 1/5] clk: qcom: Add support for SR2 PLLs Date: Mon, 6 Jul 2015 15:15:04 -0700 Message-ID: <20150706221504.GB30412@codeaurora.org> References: <1434098519-26406-1-git-send-email-georgi.djakov@linaro.org> <1434098519-26406-2-git-send-email-georgi.djakov@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:55194 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751017AbbGFWPG (ORCPT ); Mon, 6 Jul 2015 18:15:06 -0400 Content-Disposition: inline In-Reply-To: <1434098519-26406-2-git-send-email-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Georgi Djakov Cc: agross@codeaurora.org, mturquette@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org On 06/12, Georgi Djakov wrote: > Add support for SR2 type pll operations. SR2 is optimized for Time Interval > Error (TIE) or absolute jitter. > > Signed-off-by: Georgi Djakov > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project