[PATCH v3 0/8] Add initial support for RPM clocks

[PATCH v3 0/8] Add initial support for RPM clocks

[Georgi Djakov]

This patchset adds initial support for the clocks controlled by
the RPM (Resource Power Manager) processor on Qualcomm platforms.

The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.

Until now the RPM clock controller was not supported and a hard-
coded fixed-rate clocks were registered in the drivers. Now we
try to do a smooth transition by moving the xo oscillator to DT
(where it actually belongs) and handle both cases when RPMCC is
enabled or disabled (also to avoid breakage on current boards).

Changes since v2 (https://lkml.org/lkml/2015/8/3/513)
* Addressed various comments from Stephen. Thanks!
* Added sleep sets support.
* Added a mutex in the RPM driver.
* Support both scenarios - RPMCC enabled or disabled.
* Make RPMCC more generic in order to support other SMD RPM
  based platforms.

Changes since v1 (https://lkml.org/lkml/2015/7/9/257):
* Changed the driver name to clk-smd-rpm, also build it only
  when it is needed - suggested by Srini and Bjorn.
* More detailed binding example.
* Minor changes.

Georgi Djakov (8):
  arm64: dts: qcom: 8x16: Add fixed rate on-board oscillator
  clk: qcom: msm8916: Set the parent of xo to xo_board
  clk: qcom: msm8916: Ignore sleep_clk_src registration errors
  arm64: dts: qcom: 8x16: Add fixed rate sleep clock oscillator
  clk: qcom: Add support for RPM Clocks
  clk: qcom: Add RPM clock controller driver
  clk: qcom: msm8916: Use RPMCC if it is enabled
  clk: qcom: msm8916: Remove hard-coded sleep_clk_src

 .../devicetree/bindings/clock/qcom,rpmcc.txt       |   35 +++
 arch/arm64/boot/dts/qcom/msm8916.dtsi              |   16 ++
 drivers/clk/qcom/Kconfig                           |   11 +
 drivers/clk/qcom/Makefile                          |    2 +
 drivers/clk/qcom/clk-smd-rpm.c                     |  260 ++++++++++++++++++++
 drivers/clk/qcom/clk-smd-rpm.h                     |  142 +++++++++++
 drivers/clk/qcom/gcc-msm8916.c                     |   15 +-
 drivers/clk/qcom/rpmcc.c                           |  198 +++++++++++++++
 include/dt-bindings/clock/qcom,rpmcc-msm8916.h     |   44 ++++
 9 files changed, 714 insertions(+), 9 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
 create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
 create mode 100644 drivers/clk/qcom/clk-smd-rpm.h
 create mode 100644 drivers/clk/qcom/rpmcc.c
 create mode 100644 include/dt-bindings/clock/qcom,rpmcc-msm8916.h

[PATCH v3 1/8] arm64: dts: qcom: 8x16: Add fixed rate on-board oscillator

[Georgi Djakov]

Add the on-board XO oscillator. This patch prepares for adding support
for RPM controlled clocks. In order to do smooth transition and support
both cases (RPM clock driver is enabled or nor), we first move the XO to
the DT and change the GCC fixed-rate root clock to a dummy pass-through
clock. Then if the RPM driver is enabled, we set the parent of the XO
clock in the RPM clock driver to xo_board.
The advantage of doing so is that the rate of the XO clock is not hard-
coded in the GCC driver anymore, but comes from the board layout, so
that is why it should be in DT anyway.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 8748fcca70f4..355a2acea796 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -80,6 +80,15 @@
 			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;

Re: [PATCH v3 1/8] arm64: dts: qcom: 8x16: Add fixed rate on-board oscillator

[Andy Gross]

On Tue, Oct 20, 2015 at 07:57:53PM +0300, Georgi Djakov wrote:
> Add the on-board XO oscillator. This patch prepares for adding support
> for RPM controlled clocks. In order to do smooth transition and support
> both cases (RPM clock driver is enabled or nor), we first move the XO to
> the DT and change the GCC fixed-rate root clock to a dummy pass-through
> clock. Then if the RPM driver is enabled, we set the parent of the XO
> clock in the RPM clock driver to xo_board.
> The advantage of doing so is that the rate of the XO clock is not hard-
> coded in the GCC driver anymore, but comes from the board layout, so
> that is why it should be in DT anyway.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---

Looks good to me.

Reviewed-by: Andy Gross <agross@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 1/8] arm64: dts: qcom: 8x16: Add fixed rate on-board oscillator

[Stephen Boyd]

On 10/20, Georgi Djakov wrote:
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 8748fcca70f4..355a2acea796 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -80,6 +80,15 @@
>  			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>  	};
>  
> +	clocks {
> +		xo_board: xo_board {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <19200000>;
> +			clock-output-names = "xo_board";

clock-output-names isn't necessary here because the node name is
the same and we use that by default.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 2/8] clk: qcom: msm8916: Set the parent of xo to xo_board

[Georgi Djakov]

Remove the hard-coded clock rate from the driver and set the XO
parent to the on-board XO oscillator that is defined in the DT.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8916.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index d0a0313d6bef..3c0668b12142 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -3360,7 +3360,7 @@ static int gcc_msm8916_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 
 	/* Temporary until RPM clocks supported */
-	clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
+	clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1);
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 

Re: [PATCH v3 2/8] clk: qcom: msm8916: Set the parent of xo to xo_board

[Stephen Boyd]

On 10/20, Georgi Djakov wrote:
> Remove the hard-coded clock rate from the driver and set the XO
> parent to the on-board XO oscillator that is defined in the DT.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
>  drivers/clk/qcom/gcc-msm8916.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
> index d0a0313d6bef..3c0668b12142 100644
> --- a/drivers/clk/qcom/gcc-msm8916.c
> +++ b/drivers/clk/qcom/gcc-msm8916.c
> @@ -3360,7 +3360,7 @@ static int gcc_msm8916_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  
>  	/* Temporary until RPM clocks supported */
> -	clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
> +	clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1);

Sorry, I'd prefer to not take any DT changes through clk tree if
we can avoid it. So we need to write some code to figure out if
the xo_board clock is present, and keep registering this clock as
the root clk if it isn't there.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 3/8] clk: qcom: msm8916: Ignore sleep_clk_src registration errors

[Georgi Djakov]

We are moving the sleep clock to the DT. While all patches
are merged, we will ignore sleep_clk_src registration errors.
By ignoring this error, the msm8916 boards will continue booting
during this transition period, otherwise the clock controller
initialization will fail.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8916.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 3c0668b12142..4bb7d8415ba7 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -3364,10 +3364,8 @@ static int gcc_msm8916_probe(struct platform_device *pdev)
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 
-	clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
-				      CLK_IS_ROOT, 32768);
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
+	clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
+				CLK_IS_ROOT, 32768);
 
 	return qcom_cc_probe(pdev, &gcc_msm8916_desc);
 }

Re: [PATCH v3 3/8] clk: qcom: msm8916: Ignore sleep_clk_src registration errors

[Stephen Boyd]

On 10/20, Georgi Djakov wrote:
> We are moving the sleep clock to the DT. While all patches
> are merged, we will ignore sleep_clk_src registration errors.
> By ignoring this error, the msm8916 boards will continue booting
> during this transition period, otherwise the clock controller
> initialization will fail.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
>  drivers/clk/qcom/gcc-msm8916.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
> index 3c0668b12142..4bb7d8415ba7 100644
> --- a/drivers/clk/qcom/gcc-msm8916.c
> +++ b/drivers/clk/qcom/gcc-msm8916.c
> @@ -3364,10 +3364,8 @@ static int gcc_msm8916_probe(struct platform_device *pdev)
>  	if (IS_ERR(clk))
>  		return PTR_ERR(clk);
>  
> -	clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
> -				      CLK_IS_ROOT, 32768);
> -	if (IS_ERR(clk))
> -		return PTR_ERR(clk);
> +	clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
> +				CLK_IS_ROOT, 32768);
>  

And we might as well do the same check here too. We can remove
the code in a year or something.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 4/8] arm64: dts: qcom: 8x16: Add fixed rate sleep clock oscillator

[Georgi Djakov]

The sleep clock oscillator should be in the DT instead of being
hard-coded into the clock drivers.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 355a2acea796..fda4d5cd574a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -87,6 +87,13 @@
 			clock-frequency = <19200000>;
 			clock-output-names = "xo_board";
 		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "sleep_clk_src";
+		};
 	};
 
 	soc: soc {

[PATCH v3 5/8] clk: qcom: Add support for RPM Clocks

[Georgi Djakov]

This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor found on some Qualcomm SoCs.

The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.

This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/Kconfig       |    3 +
 drivers/clk/qcom/Makefile      |    1 +
 drivers/clk/qcom/clk-smd-rpm.c |  260 ++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-smd-rpm.h |  142 ++++++++++++++++++++++
 4 files changed, 406 insertions(+)
 create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
 create mode 100644 drivers/clk/qcom/clk-smd-rpm.h

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83aab4f4..f06a331e9a24 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1,3 +1,6 @@
+config QCOM_CLK_SMD_RPM
+	bool
+
 config QCOM_GDSC
 	bool
 	select PM_GENERIC_DOMAINS if PM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe6252349e55..b0bc0d3d585f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += reset.o
+clk-qcom-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
new file mode 100644
index 000000000000..aa634bdf0aae
--- /dev/null
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/soc/qcom/smd-rpm.h>
+
+#include "clk-smd-rpm.h"
+
+#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
+
+static DEFINE_MUTEX(rpm_clk_lock);
+
+static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
+				       unsigned long value)
+{
+	struct clk_smd_rpm_req req = {
+		.key = r->rpm_key,
+		.nbytes = sizeof(u32),
+		.value = DIV_ROUND_UP(value, 1000), /* RPM expects kHz */
+	};
+
+	return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
+				  r->rpm_res_type, r->rpm_clk_id, &req,
+				  sizeof(req));
+}
+
+static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
+				      unsigned long value)
+{
+	struct clk_smd_rpm_req req = {
+		.key = r->rpm_key,
+		.nbytes = sizeof(u32),
+		.value = DIV_ROUND_UP(value, 1000), /* RPM expects kHz */
+	};
+
+	return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
+				  r->rpm_res_type, r->rpm_clk_id, &req,
+				  sizeof(req));
+}
+
+static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
+			    unsigned long *active, unsigned long *sleep)
+{
+	*active = rate;
+
+	/*
+	 * Active-only clocks don't care what the rate is during sleep. So,
+	 * they vote for zero.
+	 */
+	if (r->active_only)
+		*sleep = 0;
+	else
+		*sleep = *active;
+}
+
+static int clk_smd_rpm_prepare(struct clk_hw *hw)
+{
+	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+	struct clk_smd_rpm *peer = r->peer;
+	unsigned long this_rate = 0, this_sleep_rate = 0;
+	unsigned long peer_rate = 0, peer_sleep_rate = 0;
+	unsigned long active_rate, sleep_rate;
+	int ret = 0;
+
+	mutex_lock(&rpm_clk_lock);
+
+	/* Don't send requests to the RPM if the rate has not been set. */
+	if (!r->rate)
+		goto out;
+
+	to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
+
+	/* Take peer clock's rate into account only if it's enabled. */
+	if (peer->enabled)
+		to_active_sleep(peer, peer->rate,
+				&peer_rate, &peer_sleep_rate);
+
+	active_rate = max(this_rate, peer_rate);
+
+	if (r->branch)
+		active_rate = !!active_rate;
+
+	ret = clk_smd_rpm_set_rate_active(r, active_rate);
+	if (ret)
+		goto out;
+
+	sleep_rate = max(this_sleep_rate, peer_sleep_rate);
+	if (r->branch)
+		sleep_rate = !!sleep_rate;
+
+	ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
+	if (ret)
+		/* Undo the active set vote and restore it */
+		ret = clk_smd_rpm_set_rate_active(r, peer_rate);
+
+out:
+	if (!ret)
+		r->enabled = true;
+
+	mutex_unlock(&rpm_clk_lock);
+
+	return ret;
+}
+
+static void clk_smd_rpm_unprepare(struct clk_hw *hw)
+{
+	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+
+	mutex_lock(&rpm_clk_lock);
+
+	if (r->rate) {
+		struct clk_smd_rpm *peer = r->peer;
+		unsigned long peer_rate = 0, peer_sleep_rate = 0;
+		unsigned long active_rate, sleep_rate;
+		int ret;
+
+		/* Take peer clock's rate into account only if it's enabled. */
+		if (peer->enabled)
+			to_active_sleep(peer, peer->rate, &peer_rate,
+					&peer_sleep_rate);
+
+		active_rate = r->branch ? !!peer_rate : peer_rate;
+		ret = clk_smd_rpm_set_rate_active(r, active_rate);
+		if (ret)
+			goto out;
+
+		sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
+		ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
+		if (ret)
+			goto out;
+	}
+	r->enabled = false;
+
+out:
+	mutex_unlock(&rpm_clk_lock);
+}
+
+static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+	int ret = 0;
+
+	mutex_lock(&rpm_clk_lock);
+
+	if (r->enabled) {
+		struct clk_smd_rpm *peer = r->peer;
+		unsigned long active_rate, sleep_rate;
+		unsigned long this_rate = 0, this_sleep_rate = 0;
+		unsigned long peer_rate = 0, peer_sleep_rate = 0;
+
+		to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
+
+		/* Take peer clock's rate into account only if it's enabled. */
+		if (peer->enabled)
+			to_active_sleep(peer, peer->rate,
+					&peer_rate, &peer_sleep_rate);
+
+		active_rate = max(this_rate, peer_rate);
+		ret = clk_smd_rpm_set_rate_active(r, active_rate);
+		if (ret)
+			goto out;
+
+		sleep_rate = max(this_sleep_rate, peer_sleep_rate);
+		ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
+		if (ret)
+			goto out;
+	}
+	r->rate = rate;
+out:
+	mutex_unlock(&rpm_clk_lock);
+
+	return ret;
+}
+
+static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
+				   unsigned long *parent_rate)
+{
+	/*
+	 * RPM handles rate rounding and we don't have a way to
+	 * know what the rate will be, so just return whatever
+	 * rate is requested.
+	 */
+	return rate;
+}
+
+static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+
+	/*
+	 * RPM handles rate rounding and we don't have a way to
+	 * know what the rate will be, so just return whatever
+	 * rate was set.
+	 */
+	return r->rate;
+}
+
+int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
+{
+	int ret;
+	struct clk_smd_rpm_req req = {
+		.key = QCOM_RPM_SMD_KEY_ENABLE,
+		.nbytes = sizeof(u32),
+		.value = 1,
+	};
+
+	ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
+				 QCOM_SMD_RPM_MISC_CLK,
+				 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
+	if (ret) {
+		pr_err("RPM clock scaling (sleep set) not enabled!\n");
+		return ret;
+	}
+
+	ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
+				 QCOM_SMD_RPM_MISC_CLK,
+				 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
+	if (ret) {
+		pr_err("RPM clock scaling (active set) not enabled!\n");
+		return ret;
+	}
+
+	pr_debug("%s: RPM clock scaling is enabled\n", __func__);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_smd_rpm_enable_scaling);
+
+const struct clk_ops clk_smd_rpm_ops = {
+	.prepare = clk_smd_rpm_prepare,
+	.unprepare = clk_smd_rpm_unprepare,
+	.set_rate = clk_smd_rpm_set_rate,
+	.round_rate = clk_smd_rpm_round_rate,
+	.recalc_rate = clk_smd_rpm_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_smd_rpm_ops);
+
+const struct clk_ops clk_smd_rpm_branch_ops = {
+	.prepare = clk_smd_rpm_prepare,
+	.unprepare = clk_smd_rpm_unprepare,
+	.round_rate = clk_smd_rpm_round_rate,
+	.recalc_rate = clk_smd_rpm_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_smd_rpm_branch_ops);
diff --git a/drivers/clk/qcom/clk-smd-rpm.h b/drivers/clk/qcom/clk-smd-rpm.h
new file mode 100644
index 000000000000..d5dafad6b0fc
--- /dev/null
+++ b/drivers/clk/qcom/clk-smd-rpm.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_CLK_SMD_RPM_H__
+#define __QCOM_CLK_SMD_RPM_H__
+
+#include <linux/clk-provider.h>
+
+#define QCOM_RPM_KEY_SOFTWARE_ENABLE			0x6e657773
+#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY	0x62636370
+#define QCOM_RPM_SMD_KEY_RATE				0x007a484b
+#define QCOM_RPM_SMD_KEY_ENABLE				0x62616e45
+#define QCOM_RPM_SMD_KEY_STATE				0x54415453
+#define QCOM_RPM_SCALING_ENABLE_ID			0x2
+
+struct qcom_smd_rpm;
+
+struct clk_smd_rpm {
+	const int rpm_res_type;
+	const int rpm_key;
+	const int rpm_clk_id;
+	const int rpm_status_id;
+	const bool active_only;
+	bool enabled;
+	bool branch;
+	struct clk_smd_rpm *peer;
+	struct clk_hw hw;
+	unsigned long rate;
+	struct qcom_smd_rpm *rpm;
+};
+
+struct clk_smd_rpm_req {
+	__le32 key;
+	__le32 nbytes;
+	__le32 value;
+};
+
+extern const struct clk_ops clk_smd_rpm_ops;
+extern const struct clk_ops clk_smd_rpm_branch_ops;
+int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm);
+
+#define __DEFINE_CLK_SMD_RPM(_name, active, type, r_id, stat_id, dep, key) \
+	static struct clk_smd_rpm active; \
+	static struct clk_smd_rpm _name = { \
+		.rpm_res_type = (type), \
+		.rpm_clk_id = (r_id), \
+		.rpm_status_id = (stat_id), \
+		.rpm_key = (key), \
+		.peer = &active, \
+		.rate = INT_MAX, \
+		.hw.init = &(struct clk_init_data){ \
+			.ops = &clk_smd_rpm_ops, \
+			.name = #_name, \
+			.parent_names = (const char *[]){ "xo_board" }, \
+			.num_parents = 1, \
+		}, \
+	}; \
+	static struct clk_smd_rpm active = { \
+		.rpm_res_type = (type), \
+		.rpm_clk_id = (r_id), \
+		.rpm_status_id = (stat_id), \
+		.rpm_key = (key), \
+		.peer = &_name, \
+		.active_only = true, \
+		.rate = INT_MAX, \
+		.hw.init = &(struct clk_init_data){ \
+			.ops = &clk_smd_rpm_ops, \
+			.name = #active, \
+			.parent_names = (const char *[]){ "xo_board" }, \
+			.num_parents = 1, \
+		}, \
+	};
+
+#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, active, type, r_id, stat_id, r, \
+				key) \
+	static struct clk_smd_rpm active; \
+	static struct clk_smd_rpm _name = { \
+		.rpm_res_type = (type), \
+		.rpm_clk_id = (r_id), \
+		.rpm_status_id = (stat_id), \
+		.rpm_key = (key), \
+		.peer = &active, \
+		.branch = true, \
+		.rate = (r), \
+		.hw.init = &(struct clk_init_data){ \
+			.ops = &clk_smd_rpm_branch_ops, \
+			.name = #_name, \
+			.parent_names = (const char *[]){ "xo_board" }, \
+			.num_parents = 1, \
+		}, \
+	}; \
+	static struct clk_smd_rpm active = { \
+		.rpm_res_type = (type), \
+		.rpm_clk_id = (r_id), \
+		.rpm_status_id = (stat_id), \
+		.rpm_key = (key), \
+		.peer = &_name, \
+		.active_only = true, \
+		.branch = true, \
+		.rate = (r), \
+		.hw.init = &(struct clk_init_data){ \
+			.ops = &clk_smd_rpm_branch_ops, \
+			.name = #active, \
+			.parent_names = (const char *[]){ "xo_board" }, \
+			.num_parents = 1, \
+		}, \
+	};
+
+#define DEFINE_CLK_SMD_RPM(_name, active, type, r_id, dep) \
+		__DEFINE_CLK_SMD_RPM(_name, active, type, r_id, 0, dep, \
+		QCOM_RPM_SMD_KEY_RATE)
+
+#define DEFINE_CLK_SMD_RPM_BRANCH(_name, active, type, r_id, r) \
+		__DEFINE_CLK_SMD_RPM_BRANCH(_name, active, type, r_id, 0, r, \
+		QCOM_RPM_SMD_KEY_ENABLE)
+
+#define DEFINE_CLK_SMD_RPM_QDSS(_name, active, type, r_id) \
+		__DEFINE_CLK_SMD_RPM(_name, active, type, r_id, \
+		0, 0, QCOM_RPM_SMD_KEY_STATE)
+
+#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, active, r_id) \
+		__DEFINE_CLK_SMD_RPM_BRANCH(_name, active, \
+		QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
+		QCOM_RPM_KEY_SOFTWARE_ENABLE)
+
+#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, active, r_id) \
+		__DEFINE_CLK_SMD_RPM_BRANCH(_name, active, \
+		QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
+		QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
+
+#endif

Re: [PATCH v3 5/8] clk: qcom: Add support for RPM Clocks

[Stephen Boyd]

On 10/20, Georgi Djakov wrote:
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> new file mode 100644
> index 000000000000..aa634bdf0aae
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -0,0 +1,260 @@
> +
> +static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
> +				       unsigned long value)
> +{
> +	struct clk_smd_rpm_req req = {
> +		.key = r->rpm_key,
> +		.nbytes = sizeof(u32),
> +		.value = DIV_ROUND_UP(value, 1000), /* RPM expects kHz */
> +	};
> +
> +	return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
> +				  r->rpm_res_type, r->rpm_clk_id, &req,
> +				  sizeof(req));
> +}
> +
> +static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
> +				      unsigned long value)
> +{
> +	struct clk_smd_rpm_req req = {
> +		.key = r->rpm_key,
> +		.nbytes = sizeof(u32),
> +		.value = DIV_ROUND_UP(value, 1000), /* RPM expects kHz */

Don't we need to do all the cpu_to_le32() stuff on these
structures?

> +	};
> +
> +	return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
> +				  r->rpm_res_type, r->rpm_clk_id, &req,
> +				  sizeof(req));
> +}
> +
[..]
> +
> +static int clk_smd_rpm_prepare(struct clk_hw *hw)
> +{
> +	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
> +	struct clk_smd_rpm *peer = r->peer;
> +	unsigned long this_rate = 0, this_sleep_rate = 0;
> +	unsigned long peer_rate = 0, peer_sleep_rate = 0;
> +	unsigned long active_rate, sleep_rate;
> +	int ret = 0;
> +
> +	mutex_lock(&rpm_clk_lock);
> +
> +	/* Don't send requests to the RPM if the rate has not been set. */
> +	if (!r->rate)
> +		goto out;
> +
> +	to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
> +
> +	/* Take peer clock's rate into account only if it's enabled. */
> +	if (peer->enabled)
> +		to_active_sleep(peer, peer->rate,
> +				&peer_rate, &peer_sleep_rate);
> +
> +	active_rate = max(this_rate, peer_rate);
> +
> +	if (r->branch)
> +		active_rate = !!active_rate;
> +
> +	ret = clk_smd_rpm_set_rate_active(r, active_rate);
> +	if (ret)
> +		goto out;
> +
> +	sleep_rate = max(this_sleep_rate, peer_sleep_rate);
> +	if (r->branch)
> +		sleep_rate = !!sleep_rate;
> +
> +	ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
> +	if (ret)
> +		/* Undo the active set vote and restore it */
> +		ret = clk_smd_rpm_set_rate_active(r, peer_rate);
> +
> +out:
> +	if (!ret)
> +		r->enabled = true;
> +
> +	mutex_unlock(&rpm_clk_lock);
> +
> +	return ret;
> +}
> +
> +static void clk_smd_rpm_unprepare(struct clk_hw *hw)
> +{
> +	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
> +
> +	mutex_lock(&rpm_clk_lock);
> +
> +	if (r->rate) {

The style is different than the prepare path here. Why? Please
use if (!r->rate) instead and move the local variables below to
the top of the function.

> +		struct clk_smd_rpm *peer = r->peer;
> +		unsigned long peer_rate = 0, peer_sleep_rate = 0;
> +		unsigned long active_rate, sleep_rate;
> +		int ret;
> +
> +		/* Take peer clock's rate into account only if it's enabled. */
> +		if (peer->enabled)
> +			to_active_sleep(peer, peer->rate, &peer_rate,
> +					&peer_sleep_rate);
> +
> +		active_rate = r->branch ? !!peer_rate : peer_rate;
> +		ret = clk_smd_rpm_set_rate_active(r, active_rate);
> +		if (ret)
> +			goto out;
> +
> +		sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
> +		ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
> +		if (ret)
> +			goto out;
> +	}
> +	r->enabled = false;
> +
> +out:
> +	mutex_unlock(&rpm_clk_lock);
> +}
> +
> +static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
> +				unsigned long parent_rate)
> +{
> +	struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
> +	int ret = 0;
> +
> +	mutex_lock(&rpm_clk_lock);
> +
> +	if (r->enabled) {

Same comment here. De-indent the code below.

> +		struct clk_smd_rpm *peer = r->peer;
> +		unsigned long active_rate, sleep_rate;
> +		unsigned long this_rate = 0, this_sleep_rate = 0;
> +		unsigned long peer_rate = 0, peer_sleep_rate = 0;
> +
> +		to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
> +
> +		/* Take peer clock's rate into account only if it's enabled. */
> +		if (peer->enabled)
> +			to_active_sleep(peer, peer->rate,
> +					&peer_rate, &peer_sleep_rate);
> +
> +		active_rate = max(this_rate, peer_rate);
> +		ret = clk_smd_rpm_set_rate_active(r, active_rate);
> +		if (ret)
> +			goto out;
> +
> +		sleep_rate = max(this_sleep_rate, peer_sleep_rate);
> +		ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
> +		if (ret)
> +			goto out;
> +	}
> +	r->rate = rate;
> +out:
> +	mutex_unlock(&rpm_clk_lock);
> +
> +	return ret;
> +}
> +
> +
> diff --git a/drivers/clk/qcom/clk-smd-rpm.h b/drivers/clk/qcom/clk-smd-rpm.h
> new file mode 100644
> index 000000000000..d5dafad6b0fc
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-smd-rpm.h
> @@ -0,0 +1,142 @@
> +
> +#define __DEFINE_CLK_SMD_RPM(_name, active, type, r_id, stat_id, dep, key) \
> +	static struct clk_smd_rpm active; \

Can you please align the '\' at the same column on the right
side?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 6/8] clk: qcom: Add RPM clock controller driver

[Georgi Djakov]

Add support for clocks that are controlled by the RPM processor
on Qualcomm msm8916 based platforms.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 .../devicetree/bindings/clock/qcom,rpmcc.txt       |   35 ++++
 drivers/clk/qcom/Kconfig                           |    8 +
 drivers/clk/qcom/Makefile                          |    1 +
 drivers/clk/qcom/rpmcc.c                           |  198 ++++++++++++++++++++
 include/dt-bindings/clock/qcom,rpmcc-msm8916.h     |   44 +++++
 5 files changed, 286 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
 create mode 100644 drivers/clk/qcom/rpmcc.c
 create mode 100644 include/dt-bindings/clock/qcom,rpmcc-msm8916.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
new file mode 100644
index 000000000000..bd0fd0cd50dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -0,0 +1,35 @@
+Qualcomm RPM Clock Controller Binding
+------------------------------------------------
+The RPM is a dedicated hardware engine for managing the shared
+SoC resources in order to keep the lowest power profile. It
+communicates with other hardware subsystems via shared memory
+and accepts clock requests, aggregates the requests and turns
+the clocks on/off or scales them on demand.
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+			"qcom,rpmcc-msm8916"
+
+- #clock-cells : shall contain 1
+
+Example:
+	smd {
+		compatible = "qcom,smd";
+
+		rpm {
+			interrupts = <0 168 1>;
+			qcom,ipc = <&apcs 8 0>;
+			qcom,smd-edge = <15>;
+
+			rpm_requests {
+				compatible = "qcom,rpm-msm8916";
+				qcom,smd-channels = "rpm_requests";
+
+				rpmcc: qcom,rpmcc {
+					compatible = "qcom,rpmcc-msm8916";
+					#clock-cells = <1>;
+				};
+			};
+		};
+	};
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index f06a331e9a24..29aaebcdeffa 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -12,6 +12,14 @@ config COMMON_CLK_QCOM
 	select REGMAP_MMIO
 	select RESET_CONTROLLER
 
+config QCOM_RPMCC
+	tristate "Qualcomm RPM Clock Controller"
+	depends on QCOM_SMD_RPM && COMMON_CLK_QCOM
+	select QCOM_CLK_SMD_RPM
+	help
+	  Support for the clocks exposed by the Resource Power Manager
+	  processor on devices like apq8016, apq8084 and msm8974.
+
 config APQ_GCC_8084
 	tristate "APQ8084 Global Clock Controller"
 	select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b0bc0d3d585f..e58a567ddb42 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += reset.o
 clk-qcom-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
+clk-qcom-$(CONFIG_QCOM_RPMCC) += rpmcc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
diff --git a/drivers/clk/qcom/rpmcc.c b/drivers/clk/qcom/rpmcc.c
new file mode 100644
index 000000000000..88283e2c95f7
--- /dev/null
+++ b/drivers/clk/qcom/rpmcc.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/soc/qcom/smd-rpm.h>
+
+#include "clk-smd-rpm.h"
+#include <dt-bindings/clock/qcom,rpmcc-msm8916.h>
+
+#define CXO_ID			0x0
+#define QDSS_ID			0x1
+#define BUS_SCALING		0x2
+
+#define PCNOC_ID		0x0
+#define SNOC_ID			0x1
+#define BIMC_ID			0x0
+
+#define BB_CLK1_ID		0x1
+#define BB_CLK2_ID		0x2
+#define RF_CLK1_ID		0x4
+#define RF_CLK2_ID		0x5
+
+struct rpm_cc {
+	struct qcom_rpm *rpm;
+	struct clk_onecell_data data;
+	struct clk *clks[];
+};
+
+/* SMD clocks */
+DEFINE_CLK_SMD_RPM(pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, PCNOC_ID, NULL);
+DEFINE_CLK_SMD_RPM(snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, SNOC_ID, NULL);
+DEFINE_CLK_SMD_RPM(bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, BIMC_ID, NULL);
+
+DEFINE_CLK_SMD_RPM_BRANCH(xo, xo_a, QCOM_SMD_RPM_MISC_CLK, CXO_ID, 19200000);
+DEFINE_CLK_SMD_RPM_QDSS(qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, QDSS_ID);
+
+/* SMD_XO_BUFFER */
+DEFINE_CLK_SMD_RPM_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(rf_clk1, rf_clk1_a, RF_CLK1_ID);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
+
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1_pin, rf_clk1_a_pin, RF_CLK1_ID);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2_pin, rf_clk2_a_pin, RF_CLK2_ID);
+
+static struct clk_smd_rpm *rpmcc_msm8916_clks[] = {
+	[RPM_XO_CLK_SRC] = &xo,
+	[RPM_XO_A_CLK_SRC] = &xo_a,
+	[RPM_PCNOC_CLK] = &pcnoc_clk,
+	[RPM_PCNOC_A_CLK] = &pcnoc_a_clk,
+	[RPM_SNOC_CLK] = &snoc_clk,
+	[RPM_SNOC_A_CLK] = &snoc_a_clk,
+	[RPM_BIMC_CLK] = &bimc_clk,
+	[RPM_BIMC_A_CLK] = &bimc_a_clk,
+	[RPM_QDSS_CLK] = &qdss_clk,
+	[RPM_QDSS_A_CLK] = &qdss_a_clk,
+	[RPM_BB_CLK1] = &bb_clk1,
+	[RPM_BB_CLK1_A] = &bb_clk1_a,
+	[RPM_BB_CLK2] = &bb_clk2,
+	[RPM_BB_CLK2_A] = &bb_clk2_a,
+	[RPM_RF_CLK1] = &rf_clk1,
+	[RPM_RF_CLK1_A] = &rf_clk1_a,
+	[RPM_RF_CLK2] = &rf_clk2,
+	[RPM_RF_CLK2_A] = &rf_clk2_a,
+	[RPM_BB_CLK1_PIN] = &bb_clk1_pin,
+	[RPM_BB_CLK1_A_PIN] = &bb_clk1_a_pin,
+	[RPM_BB_CLK2_PIN] = &bb_clk2_pin,
+	[RPM_BB_CLK2_A_PIN] = &bb_clk2_a_pin,
+	[RPM_RF_CLK1_PIN] = &rf_clk1_pin,
+	[RPM_RF_CLK1_A_PIN] = &rf_clk1_a_pin,
+	[RPM_RF_CLK2_PIN] = &rf_clk2_pin,
+	[RPM_RF_CLK2_A_PIN] = &rf_clk2_a_pin,
+};
+
+struct rpmcc_desc {
+	struct clk_smd_rpm **clks;
+	size_t num_clks;
+};
+
+static const struct rpmcc_desc rpmcc_msm8916 = {
+	.clks = rpmcc_msm8916_clks,
+	.num_clks = ARRAY_SIZE(rpmcc_msm8916_clks),
+};
+
+static const struct of_device_id rpmcc_match_table[] = {
+	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpmcc_msm8916},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, rpmcc_match_table);
+
+static int rpmcc_probe(struct platform_device *pdev)
+{
+	struct clk **clks;
+	struct clk *clk;
+	struct clk_smd_rpm **rpm_clks;
+	struct rpm_cc *rcc;
+	const struct rpmcc_desc *desc;
+	struct qcom_smd_rpm *rpm;
+	struct clk_onecell_data *data;
+	int ret, i;
+	size_t num_clks;
+	const struct of_device_id *match;
+
+	rpm = dev_get_drvdata(pdev->dev.parent);
+	if (!rpm) {
+		dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
+		return -ENODEV;
+	}
+
+	match = of_match_device(rpmcc_match_table, &pdev->dev);
+	if (!match)
+		return -EINVAL;
+
+	desc = match->data;
+	rpm_clks = desc->clks;
+	num_clks = desc->num_clks;
+
+	rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*clks) * num_clks,
+			   GFP_KERNEL);
+	if (!rcc)
+		return -ENOMEM;
+
+	clks = rcc->clks;
+	data = &rcc->data;
+	data->clks = clks;
+	data->clk_num = num_clks;
+
+	for (i = 0; i < num_clks; i++) {
+		if (!rpm_clks[i]) {
+			clks[i] = ERR_PTR(-ENOENT);
+			continue;
+		}
+
+		rpm_clks[i]->rpm = rpm;
+		clk = devm_clk_register(&pdev->dev, &rpm_clks[i]->hw);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+
+		clks[i] = clk;
+	}
+
+	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+				  data);
+	if (ret)
+		return ret;
+
+	return clk_smd_rpm_enable_scaling(rpm);
+}
+
+static int rpmcc_remove(struct platform_device *pdev)
+{
+	of_clk_del_provider(pdev->dev.of_node);
+	return 0;
+}
+
+static struct platform_driver rpmcc_driver = {
+	.driver = {
+		.name = "qcom-rpmcc",
+		.of_match_table = rpmcc_match_table,
+	},
+	.probe = rpmcc_probe,
+	.remove = rpmcc_remove,
+};
+
+static int __init rpmcc_init(void)
+{
+	return platform_driver_register(&rpmcc_driver);
+}
+core_initcall(rpmcc_init);
+
+static void __exit rpmcc_exit(void)
+{
+	platform_driver_unregister(&rpmcc_driver);
+}
+module_exit(rpmcc_exit);
+
+MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:rpmcc");
diff --git a/include/dt-bindings/clock/qcom,rpmcc-msm8916.h b/include/dt-bindings/clock/qcom,rpmcc-msm8916.h
new file mode 100644
index 000000000000..62d63940896a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,rpmcc-msm8916.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_8916_H
+#define _DT_BINDINGS_CLK_MSM_RPMCC_8916_H
+
+#define RPM_XO_CLK_SRC				0
+#define RPM_XO_A_CLK_SRC			1
+#define RPM_PCNOC_CLK				2
+#define RPM_PCNOC_A_CLK				3
+#define RPM_SNOC_CLK				4
+#define RPM_SNOC_A_CLK				6
+#define RPM_BIMC_CLK				7
+#define RPM_BIMC_A_CLK				8
+#define RPM_QDSS_CLK				9
+#define RPM_QDSS_A_CLK				10
+#define RPM_BB_CLK1				11
+#define RPM_BB_CLK1_A				12
+#define RPM_BB_CLK2				13
+#define RPM_BB_CLK2_A				14
+#define RPM_RF_CLK1				15
+#define RPM_RF_CLK1_A				16
+#define RPM_RF_CLK2				17
+#define RPM_RF_CLK2_A				18
+#define RPM_BB_CLK1_PIN				19
+#define RPM_BB_CLK1_A_PIN			20
+#define RPM_BB_CLK2_PIN				21
+#define RPM_BB_CLK2_A_PIN			22
+#define RPM_RF_CLK1_PIN				23
+#define RPM_RF_CLK1_A_PIN			24
+#define RPM_RF_CLK2_PIN				25
+#define RPM_RF_CLK2_A_PIN			26
+
+#endif

Re: [PATCH v3 6/8] clk: qcom: Add RPM clock controller driver

[Stephen Boyd]

On 10/20, Georgi Djakov wrote:
> diff --git a/drivers/clk/qcom/rpmcc.c b/drivers/clk/qcom/rpmcc.c
> new file mode 100644
> index 000000000000..88283e2c95f7
> --- /dev/null
> +++ b/drivers/clk/qcom/rpmcc.c
> @@ -0,0 +1,198 @@
> +/*
> + * Copyright (c) 2015, Linaro Limited
> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>

Is this include used?

> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/soc/qcom/smd-rpm.h>

Is this include used?

Add init.h for __init usage.

> +
> +#include "clk-smd-rpm.h"
> +#include <dt-bindings/clock/qcom,rpmcc-msm8916.h>
[..]
> +
> +static struct clk_smd_rpm *rpmcc_msm8916_clks[] = {

Can this be const?

> +	[RPM_XO_CLK_SRC] = &xo,
> +	[RPM_XO_A_CLK_SRC] = &xo_a,
> +	[RPM_PCNOC_CLK] = &pcnoc_clk,
> +	[RPM_PCNOC_A_CLK] = &pcnoc_a_clk,
[..]
> +
> +static int rpmcc_probe(struct platform_device *pdev)
> +{
> +	struct clk **clks;
> +	struct clk *clk;
> +	struct clk_smd_rpm **rpm_clks;
> +	struct rpm_cc *rcc;
> +	const struct rpmcc_desc *desc;
> +	struct qcom_smd_rpm *rpm;
> +	struct clk_onecell_data *data;
> +	int ret, i;
> +	size_t num_clks;
> +	const struct of_device_id *match;
> +
> +	rpm = dev_get_drvdata(pdev->dev.parent);
> +	if (!rpm) {
> +		dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
> +		return -ENODEV;
> +	}
> +
> +	match = of_match_device(rpmcc_match_table, &pdev->dev);

of_device_get_match_data() please

> +	if (!match)
> +		return -EINVAL;
> +
> +	desc = match->data;
> +	rpm_clks = desc->clks;
> +	num_clks = desc->num_clks;
> +
[..]
> +	}
> +
> +	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
> +				  data);
> +	if (ret)
> +		return ret;
> +
> +	return clk_smd_rpm_enable_scaling(rpm);

We should unregister the provider if clk_smd_rpm_enable_scaling()
fails.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 7/8] clk: qcom: msm8916: Use RPMCC if it is enabled

[Georgi Djakov]

The RPM clock controller driver takes care of registering the
xo clock. Do not register it in this driver if RPM is enabled.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8916.c |   16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 4bb7d8415ba7..3e1062fed230 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -3359,13 +3359,15 @@ static int gcc_msm8916_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct device *dev = &pdev->dev;
 
-	/* Temporary until RPM clocks supported */
-	clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1);
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
-				CLK_IS_ROOT, 32768);
+	if (!IS_ENABLED(CONFIG_QCOM_RPMCC)) {
+		/* RPM clocks are not enabled */
+		clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1);
+		if (IS_ERR(clk))
+			return PTR_ERR(clk);
+
+		clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
+					CLK_IS_ROOT, 32768);
+	}
 
 	return qcom_cc_probe(pdev, &gcc_msm8916_desc);
 }

[PATCH v3 8/8] clk: qcom: msm8916: Remove hard-coded sleep_clk_src

[Georgi Djakov]

The sleep_clk_src has been moved to DT, so we do not need to
register it in the GCC driver anymore.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8916.c |    3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 3e1062fed230..6b687790fe24 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -3364,9 +3364,6 @@ static int gcc_msm8916_probe(struct platform_device *pdev)
 		clk = clk_register_fixed_factor(dev, "xo", "xo_board", 0, 1, 1);
 		if (IS_ERR(clk))
 			return PTR_ERR(clk);
-
-		clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
-					CLK_IS_ROOT, 32768);
 	}
 
 	return qcom_cc_probe(pdev, &gcc_msm8916_desc);