From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH] clk: qcom: msm8960: fix ce3_core clk enable register Date: Mon, 22 Feb 2016 12:59:03 -0800 Message-ID: <20160222205903.GU4847@codeaurora.org> References: <1456141419-7439-1-git-send-email-srinivas.kandagatla@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:52364 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754469AbcBVU7E (ORCPT ); Mon, 22 Feb 2016 15:59:04 -0500 Content-Disposition: inline In-Reply-To: <1456141419-7439-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Srinivas Kandagatla Cc: linux-clk@vger.kernel.org, Michael Turquette , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org On 02/22, Srinivas Kandagatla wrote: > This patch corrects the enable register offset which is actually 0x36cc > instead of 0x36c4 > > Signed-off-by: Srinivas Kandagatla > --- Applied to clk-next + added fixes tag -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project