From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH v2] clk: qcom: Fix pre-divider usage for pixel RCG Date: Mon, 29 Feb 2016 12:57:15 -0800 Message-ID: <20160229205715.GF28849@codeaurora.org> References: <1456464655-3684-1-git-send-email-architt@codeaurora.org> <1456654037-15787-1-git-send-email-architt@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:56688 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750755AbcB2U5R (ORCPT ); Mon, 29 Feb 2016 15:57:17 -0500 Content-Disposition: inline In-Reply-To: <1456654037-15787-1-git-send-email-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Archit Taneja Cc: linux-arm-msm@vger.kernel.org, John Stultz , Vinay Simha On 02/28, Archit Taneja wrote: > The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading > its current value from the NS register. > > Using the pre-divider wasn't really intended when creating these ops. > The pixel RCG was only intended to achieve fractional multiplication > provided in the pixel_table array. Leaving the pre-divider to the > existing register value results in a wrong pixel clock when the > bootloader sets up the display. This was left unidentified because > the IFC6410 Plus board on which this was verified didn't have a > bootloader that configured the display. > > Don't set the RCG pre-divider in freq_tbl to the existing NS register > value. Force it to 1 and only use the M/N counter to achieve the desired > fractional multiplication. > > Cc: John Stultz > Cc: Vinay Simha > Signed-off-by: Archit Taneja > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project