From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Archit Taneja <architt@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, cernekee@gmail.com,
sboyd@codeaurora.org, linux-mtd@lists.infradead.org,
dehrenberg@google.com, andy.gross@linaro.org,
computersforpeace@gmail.com
Subject: Re: [PATCH v8 2/3] mtd: nand: Qualcomm NAND controller driver
Date: Sat, 19 Mar 2016 11:34:13 +0100 [thread overview]
Message-ID: <20160319113413.1f0f3e5f@bbrezillon> (raw)
In-Reply-To: <56ED269B.5020102@codeaurora.org>
On Sat, 19 Mar 2016 15:44:51 +0530
Archit Taneja <architt@codeaurora.org> wrote:
>
>
> On 03/18/2016 10:18 PM, Boris Brezillon wrote:
> > On Fri, 18 Mar 2016 16:49:04 +0100
> > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> >
> >> Hi Archit,
> >>
> >> On Wed, 3 Feb 2016 14:29:50 +0530
> >> Archit Taneja <architt@codeaurora.org> wrote:
> >>
> >>> +/*
> >>> + * NAND controller page layout info
> >>> + *
> >>> + * Layout with ECC enabled:
> >>> + *
> >>> + * |----------------------| |---------------------------------|
> >>> + * | xx.......yy| | *********xx.......yy|
> >>> + * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy|
> >>> + * | (516) xx.......yy| | (516-n*4) **(n*4)**xx.......yy|
> >>> + * | xx.......yy| | *********xx.......yy|
> >>> + * |----------------------| |---------------------------------|
> >>> + * codeword 1,2..n-1 codeword n
> >>> + * <---(528/532 Bytes)--> <-------(528/532 Bytes)--------->
> >>> + *
> >>> + * n = Number of codewords in the page
> >>> + * . = ECC bytes
> >>> + * * = Spare/free bytes
> >>> + * x = Unused byte(s)
> >>> + * y = Reserved byte(s)
> >>> + *
> >>> + * 2K page: n = 4, spare = 16 bytes
> >>> + * 4K page: n = 8, spare = 32 bytes
> >>> + * 8K page: n = 16, spare = 64 bytes
> >>> + *
> >>> + * the qcom nand controller operates at a sub page/codeword level. each
> >>> + * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
> >>> + * the number of ECC bytes vary based on the ECC strength and the bus width.
> >>> + *
> >>> + * the first n - 1 codewords contains 516 bytes of user data, the remaining
> >>> + * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
> >>> + * both user data and spare(oobavail) bytes that sum up to 516 bytes.
> >>> + *
> >>> + * When we access a page with ECC enabled, the reserved bytes(s) are not
> >>> + * accessible at all. When reading, we fill up these unreadable positions
> >>> + * with 0xffs. When writing, the controller skips writing the inaccessible
> >>> + * bytes.
> >>> + *
> >>> + * Layout with ECC disabled:
> >>> + *
> >>> + * |------------------------------| |---------------------------------------|
> >>> + * | yy xx.......| | bb *********xx.......|
> >>> + * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..|
> >>> + * | (size1) yy (size2) xx.......| | (size1) bb (size2) **(n*4)**xx.......|
> >>> + * | yy xx.......| | bb *********xx.......|
> >>> + * |------------------------------| |---------------------------------------|
> >>> + * codeword 1,2..n-1 codeword n
> >>> + * <-------(528/532 Bytes)------> <-----------(528/532 Bytes)----------->
> >>> + *
> >>> + * n = Number of codewords in the page
> >>> + * . = ECC bytes
> >>> + * * = Spare/free bytes
> >>> + * x = Unused byte(s)
> >>> + * y = Dummy Bad Bock byte(s)
> >>> + * b = Real Bad Block byte(s)
> >>> + * size1/size2 = function of codeword size and 'n'
> >>> + *
> >>> + * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
> >>> + * width) is now accessible. For the first n - 1 codewords, these are dummy Bad
> >>> + * Block Markers. In the last codeword, this position contains the real BBM
> >>> + *
> >>> + * In order to have a consistent layout between RAW and ECC modes, we assume
> >>> + * the following OOB layout arrangement:
> >>> + *
> >>> + * |-----------| |--------------------|
> >>> + * |yyxx.......| |bb*********xx.......|
> >>> + * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..|
> >>> + * |yyxx.......| |bb*********xx.......|
> >>> + * |yyxx.......| |bb*********xx.......|
> >>> + * |-----------| |--------------------|
> >>> + * first n - 1 nth OOB region
> >>> + * OOB regions
> >>> + *
> >>> + * n = Number of codewords in the page
> >>> + * . = ECC bytes
> >>> + * * = FREE OOB bytes
> >>> + * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
> >>> + * x = Unused byte(s)
> >>> + * b = Real bad block byte(s) (inaccessible when ECC enabled)
> >>> + *
> >>> + * This layout is read as is when ECC is disabled. When ECC is enabled, the
> >>> + * inaccessible Bad Block byte(s) are ignored when we write to a page/oob,
> >>> + * and assumed as 0xffs when we read a page/oob. The ECC, unused and
> >>> + * dummy/real bad block bytes are grouped as ecc bytes in nand_ecclayout (i.e,
> >>> + * ecc->bytes is the sum of the three).
> >>> + */
> >>> +
> >>> +static struct nand_ecclayout *
> >>> +qcom_nand_create_layout(struct qcom_nand_host *host)
> >>> +{
> >>> + struct nand_chip *chip = &host->chip;
> >>> + struct mtd_info *mtd = nand_to_mtd(chip);
> >>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> >>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
> >>> + struct nand_ecclayout *layout;
> >>> + int i, j, steps, pos = 0, shift = 0;
> >>> +
> >>> + layout = devm_kzalloc(nandc->dev, sizeof(*layout), GFP_KERNEL);
> >>> + if (!layout)
> >>> + return NULL;
> >>> +
> >>> + steps = mtd->writesize / ecc->size;
> >>> + layout->eccbytes = steps * ecc->bytes;
> >>> +
> >>> + layout->oobfree[0].offset = (steps - 1) * ecc->bytes + host->bbm_size;
> >>> + layout->oobfree[0].length = steps << 2;
> >>> + layout->oobavail = steps << 2;
> >>> +
> >>> + /*
> >>> + * the oob bytes in the first n - 1 codewords are all grouped together
> >>> + * in the format:
> >>> + * DUMMY_BBM + UNUSED + ECC
> >>> + */
> >>> + for (i = 0; i < steps - 1; i++) {
> >>> + for (j = 0; j < ecc->bytes; j++)
> >>> + layout->eccpos[pos++] = i * ecc->bytes + j;
> >>> + }
> >>> +
> >>> + /*
> >>> + * the oob bytes in the last codeword are grouped in the format:
> >>> + * BBM + FREE OOB + UNUSED + ECC
> >>> + */
> >>> +
> >>> + /* fill up the bbm positions */
> >>> + for (j = 0; j < host->bbm_size; j++)
> >>> + layout->eccpos[pos++] = i * ecc->bytes + j;
> >>> +
> >>> + /*
> >>> + * fill up the ecc and reserved positions, their indices are offseted
> >>> + * by the free oob region
> >>> + */
> >>> + shift = layout->oobfree[0].length + host->bbm_size;
> >>> +
> >>> + for (j = 0; j < (host->ecc_bytes_hw + host->spare_bytes); j++)
> >>> + layout->eccpos[pos++] = i * ecc->bytes + shift + j;
> >>> +
> >>> + return layout;
> >>> +}
> >>
> >> I'm trying to move this layout definition to the mtd_ooblayout_ops
> >> approach, and I wonder why you decided to take such a complicated
> >> representation.
> >> AFAIU, in each ECC step you have 512 bytes of data, X ECC+reserved
> >> bytes (you decided to consider all of them as ECC bytes, which is fine
> >> by me) and 4 usable/free bytes. Am I correct?
> >>
> >> If that's the case, then why not exposing the following layout.
> >>
> >> eccregion[i] = {
> >> .offset = i * (ecc->bytes + 4);
> >> .length = ecc->bytes;
> >> }
> >>
> >> oobfreeregion[i] = {
> >> .offset = (i * (ecc->bytes + 4)) + ecc->bytes;
> >> .length = 4;
> >> }
> >>
> >> Are there any userspace tools relying on the ooblayout you're currently
> >> exposing (remember that the exposed OOB layout is not necessarily
> >> what you see on the media)?
> >
> > Okay, I think we already had this discussion :).
> > I'm still not happy with the exposed layout (it would be much easier to
> > reserve 4 free bytes per chunk, and declare each chunk as containing 512
> > data bytes + 4 oob bytes + X ECC/reserved bytes), but IIRC, your ROM
> > code (and/or bootloader) is already using this layout :-(.
>
> Sadly, yeah. The reason given for this was that if a filesystem only
> wanted to read the 16 oob bytes off the page, it could just read the
> last subpage instead of going through all pages. The optimization
> clearly doesn't seem worth the software overhead.
>
> Is this something that's blocking your mtd_ooblayout_ops work?
Nope, I think I got it right, but maybe you can check/test it.
Here is my branch containing the whole rework [1], and here are
the qcom relate patches[2][3].
Thanks,
Boris
[1]https://github.com/bbrezillon/linux-0day/commits/nand/ecclayout
[2]https://github.com/bbrezillon/linux-0day/commit/85fba29f4177fbbe8e43cabf433848947bd1c311
[3]https://github.com/bbrezillon/linux-0day/commit/2ebab1c79d275e32a049f293aac2d5e918ef37ab
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
next prev parent reply other threads:[~2016-03-19 10:34 UTC|newest]
Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-16 14:48 [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-01-16 14:48 ` [PATCH 1/5] clk: qcom: Add EBI2 clocks for IPQ806x Archit Taneja
2015-01-16 21:56 ` Stephen Boyd
2015-01-19 10:32 ` Archit Taneja
2015-01-29 22:21 ` Stephen Boyd
2015-01-16 14:48 ` [PATCH 2/5] mtd: nand: Add qcom nand controller driver Archit Taneja
2015-01-21 0:54 ` Daniel Ehrenberg
2015-01-22 6:36 ` Archit Taneja
2015-01-26 21:05 ` Kevin Cernekee
2015-01-27 3:56 ` Archit Taneja
[not found] ` <1421419702-17812-1-git-send-email-architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-01-16 14:48 ` [PATCH 3/5] Documentaion: dt: add DT bindings for Qualcomm NAND controller Archit Taneja
2015-01-16 14:48 ` [PATCH 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-01-16 14:48 ` [PATCH 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 pplatform Archit Taneja
2015-02-18 6:03 ` [PATCH 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-07-21 10:34 ` [PATCH v2 " Archit Taneja
2015-07-21 10:34 ` [PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-07-24 19:01 ` Andy Gross
2015-07-21 10:34 ` [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-07-24 19:39 ` Andy Gross
2015-07-25 0:51 ` Stephen Boyd
2015-07-28 4:34 ` Archit Taneja
2015-07-29 1:48 ` Stephen Boyd
2015-07-29 5:14 ` Archit Taneja
2015-07-29 18:33 ` Stephen Boyd
2015-07-30 6:53 ` Archit Taneja
2015-07-21 10:34 ` [PATCH v2 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-07-24 18:57 ` Andy Gross
2015-07-24 19:37 ` Stephen Boyd
2015-07-21 10:34 ` [PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-07-24 19:01 ` Andy Gross
2015-07-21 10:34 ` [PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform Archit Taneja
2015-07-24 18:58 ` Andy Gross
2015-07-24 18:59 ` Andy Gross
2015-08-03 5:08 ` [PATCH v3 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-03 5:08 ` [PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-08-03 5:08 ` [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-08-03 23:38 ` Stephen Boyd
2015-08-04 15:04 ` Archit Taneja
2015-08-04 17:53 ` Stephen Boyd
2015-08-03 5:08 ` [PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-08-03 5:08 ` [PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
[not found] ` <1438578498-32254-1-git-send-email-architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-08-03 5:08 ` [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
2015-08-03 19:35 ` Andy Gross
2015-08-04 15:05 ` Archit Taneja
2015-08-03 20:58 ` Stephen Boyd
2015-08-04 15:06 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 0/5] mtd: Qualcomm NAND controller driver Archit Taneja
2015-08-19 4:49 ` [PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode Archit Taneja
2015-10-02 2:44 ` Brian Norris
2015-10-02 6:27 ` Boris Brezillon
2015-10-11 20:03 ` Brian Norris
2015-11-10 5:13 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2015-08-26 23:37 ` Stephen Boyd
2015-09-13 13:42 ` Archit Taneja
2015-10-02 3:05 ` Brian Norris
2015-10-05 6:51 ` Archit Taneja
2015-10-06 9:17 ` Brian Norris
2015-10-07 4:11 ` Archit Taneja
2015-10-02 17:31 ` Brian Norris
2015-12-16 9:15 ` Boris Brezillon
2015-12-16 11:57 ` Archit Taneja
2015-12-16 14:18 ` Boris Brezillon
2015-12-17 9:48 ` Archit Taneja
2015-12-18 18:48 ` Boris Brezillon
2015-12-16 19:16 ` Brian Norris
2015-08-19 4:49 ` [PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2015-12-16 6:33 ` Boris Brezillon
2015-12-16 8:11 ` Archit Taneja
2015-08-19 4:49 ` [PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x Archit Taneja
2015-08-19 4:49 ` [PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform Archit Taneja
2016-01-05 5:24 ` [PATCH v5 0/3] mtd: Qualcomm NAND controller driver Archit Taneja
2016-01-05 5:24 ` [PATCH v5 1/3] mtd: nand: don't select chip in nand_chip's block_bad op Archit Taneja
2016-01-06 16:05 ` Boris Brezillon
2016-01-07 4:27 ` Archit Taneja
2016-01-05 5:25 ` [PATCH v5 2/3] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2016-01-06 17:05 ` Boris Brezillon
2016-01-08 6:33 ` Archit Taneja
2016-01-08 8:01 ` Boris Brezillon
2016-01-08 10:23 ` Archit Taneja
2016-01-08 10:31 ` Boris Brezillon
2016-01-08 10:42 ` Archit Taneja
2016-01-05 5:25 ` [PATCH v5 3/3] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2016-01-06 15:05 ` Boris Brezillon
2016-01-06 15:14 ` Rob Herring
2016-01-06 15:37 ` Boris Brezillon
2016-01-06 16:13 ` Rob Herring
2016-01-06 16:36 ` Boris Brezillon
2016-01-18 9:50 ` [PATCH v6 0/3] mtd: Qualcomm NAND controller driver Archit Taneja
2016-01-18 9:50 ` [PATCH v6 1/3] mtd: nand: don't select chip in nand_chip's block_bad op Archit Taneja
2016-01-18 10:29 ` Boris Brezillon
2016-01-18 10:47 ` Archit Taneja
2016-01-18 9:50 ` [PATCH v6 2/3] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2016-01-18 11:01 ` Boris Brezillon
2016-01-18 11:14 ` Archit Taneja
2016-01-18 9:50 ` [PATCH v6 3/3] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2016-01-20 14:46 ` Rob Herring
2016-01-21 7:13 ` [PATCH v7 0/3] mtd: Qualcomm NAND controller driver Archit Taneja
2016-01-21 7:13 ` [PATCH v7 1/3] mtd: nand: don't select chip in nand_chip's block_bad op Archit Taneja
2016-01-21 8:33 ` Boris Brezillon
2016-01-21 7:13 ` [PATCH v7 2/3] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2016-01-21 8:51 ` Boris Brezillon
2016-01-21 9:52 ` Archit Taneja
2016-01-21 10:13 ` Boris Brezillon
2016-01-21 11:00 ` Archit Taneja
2016-01-21 12:36 ` Boris Brezillon
2016-01-21 13:08 ` Archit Taneja
2016-01-21 13:25 ` Boris Brezillon
2016-01-25 7:43 ` Archit Taneja
2016-01-21 7:13 ` [PATCH v7 3/3] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2016-01-21 7:23 ` Archit Taneja
2016-02-03 8:59 ` [PATCH v8 0/3] mtd: Qualcomm NAND controller driver Archit Taneja
2016-02-03 8:59 ` [PATCH v8 1/3] mtd: nand: don't select chip in nand_chip's block_bad op Archit Taneja
2016-02-03 8:59 ` [PATCH v8 2/3] mtd: nand: Qualcomm NAND controller driver Archit Taneja
2016-02-04 10:39 ` Boris Brezillon
2016-02-04 16:13 ` Archit Taneja
2016-02-16 6:50 ` Archit Taneja
2016-03-08 10:13 ` Archit Taneja
2016-03-18 15:49 ` Boris Brezillon
2016-03-18 16:48 ` Boris Brezillon
2016-03-19 10:14 ` Archit Taneja
2016-03-19 10:34 ` Boris Brezillon [this message]
2016-03-22 13:10 ` Archit Taneja
2016-03-22 14:05 ` Boris Brezillon
2016-02-03 8:59 ` [PATCH v8 3/3] dt/bindings: qcom_nandc: Add DT bindings Archit Taneja
2016-03-10 19:47 ` [PATCH v8 0/3] mtd: Qualcomm NAND controller driver Brian Norris
2016-03-16 5:43 ` Archit Taneja
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