From mboxrd@z Thu Jan  1 00:00:00 1970
From: Guenter Roeck <linux@roeck-us.net>
Subject: Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog
 not in timer block
Date: Mon, 28 Mar 2016 14:56:38 -0700
Message-ID: <20160328215638.GA25221@roeck-us.net>
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To: Matthew McClintock <mmcclint@codeaurora.org>
Cc: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, "qca-upstream.external" <qca-upstream.external@qca.qualcomm.com>, Wim Van Sebroeck <wim@iguana.be>, "open list:WATCHDOG DEVICE DRIVERS" <linux-watchdog@vger.kernel.org>, open list <linux-kernel@vger.kernel.org>

On Mon, Mar 28, 2016 at 03:40:58PM -0500, Matthew McClintock wrote:
> On Mar 28, 2016, at 1:13 PM, Guenter Roeck <linux@roeck-us.net> wrote=
:
> >=20
> >>> bit 0 is the enable bit, and bit 1 enables interrupts. At address=
 0x08 (eg
> >>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and=
 bit 1 is
> >>> undefined.
> >>=20
> >> I honestly don=E2=80=99t see anything at 0x8 for either blocks tha=
t looks like this. For the new block bit 0 is enabling and bit 1 enable=
d interrupts.
> >>=20
> > That is from the APQ8064 datasheet.=20
>=20
> So taken from the timer offset 0x0208A000 I just have a generic count=
er register CPU0_APCS_GPT0_CNT at 0x8
>=20
> What doc are you looking at?
>=20
"Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Descriptio=
n"

It is available for download from the Qualcomm web site.

See chapter 12.10.3, "Watchdog timer registers". The register block is =
at
0x28882000. Registers are almost the same, except for the offset and th=
e
definition of the bits in the enable register.

LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog.

Guenter