From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH v2] arm64: dts: qcom: Fix broken interrupt trigger settings Date: Thu, 11 Aug 2016 15:19:48 -0700 Message-ID: <20160811221948.GL2996@codeaurora.org> References: <1470937850-10492-1-git-send-email-marc.zyngier@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:42444 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751443AbcHKWTu (ORCPT ); Thu, 11 Aug 2016 18:19:50 -0400 Content-Disposition: inline In-Reply-To: <1470937850-10492-1-git-send-email-marc.zyngier@arm.com> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Marc Zyngier Cc: Andy Gross , David Brown , "Ivan T. Ivanov" , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org On 08/11, Marc Zyngier wrote: > When a device uses the GIC as its interrupt controller and generates > SPIs, only the values 1 (edge rising) and 4 (level high) are legal. > > Anything else is just plain wrong (can't be programmed into the HW), > and leads to aborted driver probes (USB doesn't work with 4.8-rc1 > on a Dragonboard 410C). > > Signed-off-by: Marc Zyngier > --- Reviewed-by: Stephen Boyd -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project