From: Stephen Boyd <sboyd@codeaurora.org>
To: Rajendra Nayak <rnayak@codeaurora.org>
Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
tdas@codeaurora.org
Subject: Re: [PATCH v2 10/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update
Date: Tue, 23 Aug 2016 23:26:13 -0700 [thread overview]
Message-ID: <20160824062613.GW6502@codeaurora.org> (raw)
In-Reply-To: <1470904858-11930-11-git-send-email-rnayak@codeaurora.org>
On 08/11, Rajendra Nayak wrote:
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 2184dc1..68c90f3 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -113,6 +113,11 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, u32 mask)
> #define PLL_OFFLINE_ACK BIT(28)
> #define PLL_ACTIVE_FLAG BIT(30)
>
> +/* alpha pll with dynamic update support */
> +#define PLL_UPDATE BIT(22)
> +#define PLL_HW_LOGIC_BYPASS BIT(23)
> +#define PLL_ACK_LATCH BIT(29)
These need to move next to associated registers.
> +
> void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> const struct alpha_pll_config *config)
> {
> @@ -366,6 +402,7 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long prate)
> {
> + int enabled;
bool
> struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> const struct pll_vco *vco;
> u32 l, off = pll->offset;
> @@ -378,6 +415,11 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> return -EINVAL;
> }
>
> + enabled = hw->init->ops->is_enabled(hw);
We have clk_hw_is_enabled() for this.
> +
> + if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled)
> + hw->init->ops->disable(hw);
Please call the function directly instead of going through the
init structure to get the clk ops.
> +
> a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
>
> regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
> @@ -391,6 +433,12 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
> PLL_ALPHA_EN);
>
> + if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled)
> + hw->init->ops->enable(hw);
> +
> + if (pll->flags & SUPPORTS_DYNAMIC_UPDATE)
> + clk_alpha_pll_dynamic_update(pll);
> +
Perhaps write it as
if (pll->flags & SUPPORTS_DYNAMIC_UPDATE)
clk_alpha_pll_dynamic_update()
else if (enabled)
toggle the enable bit...
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-08-24 6:26 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-11 8:40 [PATCH v2 00/10] clk: qcom: PLL updates Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 01/10] clk: Fix inconsistencies in usage of data types Rajendra Nayak
2016-08-13 0:59 ` Stephen Boyd
2016-08-11 8:40 ` [PATCH v2 02/10] clk: qcom: Add support for alpha pll hwfsm ops Rajendra Nayak
2016-08-24 6:13 ` Stephen Boyd
2016-08-25 9:05 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 03/10] clk: qcom: Add support to initialize alpha plls Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode Rajendra Nayak
2016-08-24 6:15 ` Stephen Boyd
2016-08-25 9:12 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 05/10] clk: qcom: Add support for PLLs with early output Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 06/10] clk: qcom: Add support for PLLs supporting dynamic reprogramming Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 07/10] clk: qcom: Add support to enable FSM mode for votable alpha PLLs Rajendra Nayak
2016-08-24 6:31 ` Stephen Boyd
2016-08-25 9:16 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 08/10] clk: qcom: Cleanup some macro defs Rajendra Nayak
2016-08-13 0:57 ` Stephen Boyd
2016-08-11 8:40 ` [PATCH v2 09/10] clk: qcom: Add .is_enabled ops for clk-alpha-pll Rajendra Nayak
2016-08-24 6:28 ` Stephen Boyd
2016-08-25 9:15 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 10/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update Rajendra Nayak
2016-08-24 6:26 ` Stephen Boyd [this message]
2016-08-25 9:13 ` Rajendra Nayak
2016-08-24 6:17 ` [PATCH v2 00/10] clk: qcom: PLL updates Stephen Boyd
2016-08-25 9:17 ` Rajendra Nayak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160824062613.GW6502@codeaurora.org \
--to=sboyd@codeaurora.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=rnayak@codeaurora.org \
--cc=tdas@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).