* [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
@ 2016-09-08 13:41 Linus Walleij
2016-09-08 13:52 ` Arnd Bergmann
0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2016-09-08 13:41 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA, Andy Gross, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann
Cc: Stephen Boyd, Bjorn Andersson, David Brown, Linus Walleij
The SMSC9112 ethernet controller is connected to chip select 2
on the EBI2 bus on the APQ8060 Dragonboard. We set this up by
activating EBI2, creating a chipselect entry as a subnode, and then
putting the ethernet controller in a subnode of the chipselect.
After the chipselect is configured, the SMSC device will be
instantiated.
Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
ChangeLog v2->v3:
- Name chipselected device to ethernet-ebi2@2,0
- Update to the latest (v5) version of the bindings and what
the EBI2 driver expects.
- The SMSC911x bindings were ACKed by Arnd Bergmann and are merged
to the netdev tree by David Miller.
- The EBI2 bindings were ACKed by Rob Herring and a pull request
for both bindings and driver is pending for ARM SoC.
- This should be safe to merge for v4.9.
ChangeLog v1->v2:
- Use the new bindings with the first address cell indicating
the chipselect
- Use offset zero into the range in the EBI2 node (the range
defines the base address of the chipselect)
- Move all the XMEM setup to arrays in the EBI2 node
---
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 124 +++++++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 0abc93e5bb00..75a11cf75cbc 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -51,6 +51,29 @@
regulator-boot-on;
};
+ /* GPIO controlled ethernet power regulator */
+ dragon_veth: xc622a331mrg {
+ compatible = "regulator-fixed";
+ regulator-name = "XC6222A331MR-G";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vph>;
+ gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_veth_gpios>;
+ regulator-always-on;
+ };
+
+ /* VDDvario fixed regulator */
+ dragon_vario: nds332p {
+ compatible = "regulator-fixed";
+ regulator-name = "NDS332P";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&pm8058_s3>;
+ };
+
/* This is a levelshifter for SDCC5 */
dragon_vio_txb: txb0104rgyr {
compatible = "regulator-fixed";
@@ -167,6 +190,41 @@
bias-pull-up;
};
};
+
+ dragon_ebi2_pins: ebi2 {
+ /*
+ * Pins used by EBI2 on the Dragonboard, actually only
+ * only CS2 is used by a real peripheral. CS0 is just
+ * routed to a test point.
+ */
+ mux0 {
+ /*
+ * Pins used by EBI2 on the Dragonboard, actually only
+ * only CS2 is used by a real peripheral. CS0 is just
+ * routed to a test point.
+ */
+ pins =
+ /* "gpio39", CS1A_N this is not good to mux */
+ "gpio40", /* CS2A_N */
+ "gpio134"; /* CS0_N testpoint TP29 */
+ function = "ebi2cs";
+ };
+ mux1 {
+ pins =
+ /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
+ "gpio123", "gpio124", "gpio125", "gpio126",
+ "gpio127", "gpio128", "gpio129", "gpio130",
+ /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
+ "gpio135", "gpio136", "gpio137", "gpio138",
+ "gpio139", "gpio140", "gpio141", "gpio142",
+ "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150",
+ "gpio151", /* EBI2_OE_N */
+ "gpio153", /* EBI2_ADV */
+ "gpio157"; /* EBI2_WE_N */
+ function = "ebi2";
+ };
+ };
};
qcom,ssbi@500000 {
@@ -201,6 +259,15 @@
};
gpio@150 {
+ dragon_ethernet_gpios: ethernet-gpios {
+ pinconf {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
dragon_bmp085_gpios: bmp085-gpios {
pinconf {
pins = "gpio16";
@@ -238,6 +305,14 @@
power-source = <PM8058_GPIO_S3>;
};
};
+ dragon_veth_gpios: veth-gpios {
+ pinconf {
+ pins = "gpio40";
+ function = "normal";
+ bias-disable;
+ drive-push-pull;
+ };
+ };
};
};
};
@@ -283,6 +358,55 @@
};
};
+ ebi2@1a100000 {
+ /* The EBI2 will instantiate first, then populate its children */
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ebi2_pins>;
+
+ /*
+ * An on-board SMSC LAN9221 chip for "debug ethernet",
+ * which is actually just an ordinary ethernet on the
+ * EBI2. This has a 25MHz chrystal next to it, so no
+ * clocking is needed.
+ */
+ ethernet-ebi2@2,0 {
+ compatible = "smsc,lan9221", "smsc,lan9115";
+ reg = <2 0x0 0x100>;
+ /*
+ * GPIO7 has interrupt 198 on the PM8058
+ * The second interrupt is the PME interrupt
+ * for network wakeup, connected to the TLMM.
+ */
+ interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
+ <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ vdd33a-supply = <&dragon_veth>;
+ vddvario-supply = <&dragon_vario>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ethernet_gpios>;
+ phy-mode = "mii";
+ reg-io-width = <2>;
+ smsc,force-external-phy;
+ /* IRQ on edge falling = active low */
+ smsc,irq-active-low;
+ smsc,irq-push-pull;
+
+ /*
+ * SLOW chipselect config
+ * Delay 9 cycles (140ns@64MHz) between SMSC
+ * LAN9221 Ethernet controller reads and writes
+ * on CS2.
+ */
+ qcom,xmem-recovery-cycles = <0>;
+ qcom,xmem-write-hold-cycles = <3>;
+ qcom,xmem-write-delta-cycles = <31>;
+ qcom,xmem-read-delta-cycles = <28>;
+ qcom,xmem-write-wait-cycles = <9>;
+ qcom,xmem-read-wait-cycles = <9>;
+ };
+ };
+
rpm@104000 {
/*
* Set up of the PMIC RPM regulators for this board
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
2016-09-08 13:41 Linus Walleij
@ 2016-09-08 13:52 ` Arnd Bergmann
2016-09-08 14:03 ` Linus Walleij
0 siblings, 1 reply; 6+ messages in thread
From: Arnd Bergmann @ 2016-09-08 13:52 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Linus Walleij, linux-arm-msm, linux-soc, Andy Gross, Rob Herring,
devicetree, David Brown, Stephen Boyd, Bjorn Andersson
On Thursday, September 8, 2016 3:41:43 PM CEST Linus Walleij wrote:
> The SMSC9112 ethernet controller is connected to chip select 2
> on the EBI2 bus on the APQ8060 Dragonboard. We set this up by
> activating EBI2, creating a chipselect entry as a subnode, and then
> putting the ethernet controller in a subnode of the chipselect.
>
> After the chipselect is configured, the SMSC device will be
> instantiated.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
One more thing I noticed recently is that we still have some
hardcoded configuration in the driver:
#ifdef CONFIG_ARCH_PXA
#define SMC_USE_PXA_DMA 1
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
#define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
#define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
#elif defined(CONFIG_ARCH_OMAP3)
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
#define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
#define SMC_MEM_RESERVED 1
#elif defined(CONFIG_ARCH_OMAP2)
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
#define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
#define SMC_MEM_RESERVED 1
#else
/*
* Default configuration
*/
#define SMC_DYNAMIC_BUS_CONFIG
#endif
and I suspect we have to convert the OMAP2/OMAP3 portion here to use
dynamic configuration, otherwise things may go wrong in a multiplatform
kernel.
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
2016-09-08 13:52 ` Arnd Bergmann
@ 2016-09-08 14:03 ` Linus Walleij
2016-09-08 14:32 ` Arnd Bergmann
0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2016-09-08 14:03 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-soc, Andy Gross, Rob Herring,
devicetree@vger.kernel.org, David Brown, Stephen Boyd,
Bjorn Andersson
On Thu, Sep 8, 2016 at 3:52 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday, September 8, 2016 3:41:43 PM CEST Linus Walleij wrote:
>> The SMSC9112 ethernet controller is connected to chip select 2
>> on the EBI2 bus on the APQ8060 Dragonboard. We set this up by
>> activating EBI2, creating a chipselect entry as a subnode, and then
>> putting the ethernet controller in a subnode of the chipselect.
>>
>> After the chipselect is configured, the SMSC device will be
>> instantiated.
>>
>> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>> ---
>
> One more thing I noticed recently is that we still have some
> hardcoded configuration in the driver:
>
> #ifdef CONFIG_ARCH_PXA
> #define SMC_USE_PXA_DMA 1
> #define SMC_USE_16BIT 0
> #define SMC_USE_32BIT 1
> #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
> #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
> #define SMC_USE_16BIT 0
> #define SMC_USE_32BIT 1
> #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
> #elif defined(CONFIG_ARCH_OMAP3)
> #define SMC_USE_16BIT 0
> #define SMC_USE_32BIT 1
> #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
> #define SMC_MEM_RESERVED 1
> #elif defined(CONFIG_ARCH_OMAP2)
> #define SMC_USE_16BIT 0
> #define SMC_USE_32BIT 1
> #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
> #define SMC_MEM_RESERVED 1
> #else
> /*
> * Default configuration
> */
>
> #define SMC_DYNAMIC_BUS_CONFIG
> #endif
>
> and I suspect we have to convert the OMAP2/OMAP3 portion here to use
> dynamic configuration, otherwise things may go wrong in a multiplatform
> kernel.
Yes, but that is not the driver enabled by this patch. This is
compatible = "smsc,lan9221", "smsc,lan9115";
which has the driver smsc911x.c, but the problem
you're pointing to is in the driver smc911x.c.
or rather its header file.
One letter difference I know, the naming of these
drivers is not human-friendly. I make the mistake
all the time.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
2016-09-08 14:03 ` Linus Walleij
@ 2016-09-08 14:32 ` Arnd Bergmann
0 siblings, 0 replies; 6+ messages in thread
From: Arnd Bergmann @ 2016-09-08 14:32 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Linus Walleij, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, Stephen Boyd, Bjorn Andersson,
David Brown, Rob Herring, Andy Gross, linux-soc
On Thursday, September 8, 2016 4:03:38 PM CEST Linus Walleij wrote:
>
> Yes, but that is not the driver enabled by this patch. This is
> compatible = "smsc,lan9221", "smsc,lan9115";
> which has the driver smsc911x.c, but the problem
> you're pointing to is in the driver smc911x.c.
> or rather its header file.
>
> One letter difference I know, the naming of these
> drivers is not human-friendly. I make the mistake
> all the time.
Ah, right. I also see now that the last user of smc911x was removed
from the kernel in January 2015 with a521422ea4ae ("ARM: shmobile:
mackerel: Remove Legacy C board code"), and everything is now using
the smsc911x driver, so I suppose we can finally delete the old one
as planned originally:
commit fd9abb3d97c2ab883e4732ec1214fe64190236e7
Author: Steve Glendinning <steve.glendinning@smsc.com>
Date: Wed Nov 5 00:35:37 2008 +0000
SMSC LAN911x and LAN921x vendor driver
Attached is a driver for SMSC's LAN911x and LAN921x families of embedded
ethernet controllers.
There is an existing smc911x driver in the tree; this is intended to
replace it. Dustin McIntire (the author of the smc911x driver) has
expressed his support for switching to this driver.
This driver contains workarounds for all known hardware issues, and has
been tested on all flavours of the chip on multiple architectures.
This driver now uses phylib, so this patch also adds support for the
device's internal phy
Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: Bahadir Balban <Bahadir.Balban@arm.com>
Signed-off-by: Dustin Mcintire <dustin@sensoria.com>
Signed-off-by: Bill Gatliff <bgat@billgatliff.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
@ 2016-10-18 7:25 Linus Walleij
2016-10-19 0:52 ` Stephen Boyd
0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2016-10-18 7:25 UTC (permalink / raw)
To: linux-arm-kernel, linux-arm-msm, Andy Gross
Cc: Stephen Boyd, Bjorn Andersson, David Brown, Linus Walleij
The SMSC9112 ethernet controller is connected to chip select 2
on the EBI2 bus on the APQ8060 Dragonboard. We set this up by
activating EBI2, creating a chipselect entry as a subnode, and then
putting the ethernet controller in a subnode of the chipselect.
After the chipselect is configured, the SMSC device will be
instantiated.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v3->v4:
- Rebase on kernel v4.9-rc1
- Bindings and driver are merged so should be clear to apply.
ChangeLog v2->v3:
- Name chipselected device to ethernet-ebi2@2,0
- Update to the latest (v5) version of the bindings and what
the EBI2 driver expects.
- The SMSC911x bindings were ACKed by Arnd Bergmann and are merged
to the netdev tree by David Miller.
- The EBI2 bindings were ACKed by Rob Herring and a pull request
for both bindings and driver is pending for ARM SoC.
- This should be safe to merge for v4.9.
ChangeLog v1->v2:
- Use the new bindings with the first address cell indicating
the chipselect
- Use offset zero into the range in the EBI2 node (the range
defines the base address of the chipselect)
- Move all the XMEM setup to arrays in the EBI2 node
---
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 124 +++++++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 6c0038398ef2..7848e4c8bdb9 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -51,6 +51,29 @@
regulator-boot-on;
};
+ /* GPIO controlled ethernet power regulator */
+ dragon_veth: xc622a331mrg {
+ compatible = "regulator-fixed";
+ regulator-name = "XC6222A331MR-G";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vph>;
+ gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_veth_gpios>;
+ regulator-always-on;
+ };
+
+ /* VDDvario fixed regulator */
+ dragon_vario: nds332p {
+ compatible = "regulator-fixed";
+ regulator-name = "NDS332P";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&pm8058_s3>;
+ };
+
/* This is a levelshifter for SDCC5 */
dragon_vio_txb: txb0104rgyr {
compatible = "regulator-fixed";
@@ -167,6 +190,41 @@
bias-pull-up;
};
};
+
+ dragon_ebi2_pins: ebi2 {
+ /*
+ * Pins used by EBI2 on the Dragonboard, actually only
+ * only CS2 is used by a real peripheral. CS0 is just
+ * routed to a test point.
+ */
+ mux0 {
+ /*
+ * Pins used by EBI2 on the Dragonboard, actually only
+ * only CS2 is used by a real peripheral. CS0 is just
+ * routed to a test point.
+ */
+ pins =
+ /* "gpio39", CS1A_N this is not good to mux */
+ "gpio40", /* CS2A_N */
+ "gpio134"; /* CS0_N testpoint TP29 */
+ function = "ebi2cs";
+ };
+ mux1 {
+ pins =
+ /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
+ "gpio123", "gpio124", "gpio125", "gpio126",
+ "gpio127", "gpio128", "gpio129", "gpio130",
+ /* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
+ "gpio135", "gpio136", "gpio137", "gpio138",
+ "gpio139", "gpio140", "gpio141", "gpio142",
+ "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149", "gpio150",
+ "gpio151", /* EBI2_OE_N */
+ "gpio153", /* EBI2_ADV */
+ "gpio157"; /* EBI2_WE_N */
+ function = "ebi2";
+ };
+ };
};
qcom,ssbi@500000 {
@@ -201,6 +259,15 @@
};
gpio@150 {
+ dragon_ethernet_gpios: ethernet-gpios {
+ pinconf {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <PM8058_GPIO_S3>;
+ };
+ };
dragon_bmp085_gpios: bmp085-gpios {
pinconf {
pins = "gpio16";
@@ -238,6 +305,14 @@
power-source = <PM8058_GPIO_S3>;
};
};
+ dragon_veth_gpios: veth-gpios {
+ pinconf {
+ pins = "gpio40";
+ function = "normal";
+ bias-disable;
+ drive-push-pull;
+ };
+ };
};
led@48 {
@@ -322,6 +397,55 @@
};
};
+ ebi2@1a100000 {
+ /* The EBI2 will instantiate first, then populate its children */
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ebi2_pins>;
+
+ /*
+ * An on-board SMSC LAN9221 chip for "debug ethernet",
+ * which is actually just an ordinary ethernet on the
+ * EBI2. This has a 25MHz chrystal next to it, so no
+ * clocking is needed.
+ */
+ ethernet-ebi2@2,0 {
+ compatible = "smsc,lan9221", "smsc,lan9115";
+ reg = <2 0x0 0x100>;
+ /*
+ * GPIO7 has interrupt 198 on the PM8058
+ * The second interrupt is the PME interrupt
+ * for network wakeup, connected to the TLMM.
+ */
+ interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
+ <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ vdd33a-supply = <&dragon_veth>;
+ vddvario-supply = <&dragon_vario>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dragon_ethernet_gpios>;
+ phy-mode = "mii";
+ reg-io-width = <2>;
+ smsc,force-external-phy;
+ /* IRQ on edge falling = active low */
+ smsc,irq-active-low;
+ smsc,irq-push-pull;
+
+ /*
+ * SLOW chipselect config
+ * Delay 9 cycles (140ns@64MHz) between SMSC
+ * LAN9221 Ethernet controller reads and writes
+ * on CS2.
+ */
+ qcom,xmem-recovery-cycles = <0>;
+ qcom,xmem-write-hold-cycles = <3>;
+ qcom,xmem-write-delta-cycles = <31>;
+ qcom,xmem-read-delta-cycles = <28>;
+ qcom,xmem-write-wait-cycles = <9>;
+ qcom,xmem-read-wait-cycles = <9>;
+ };
+ };
+
rpm@104000 {
/*
* Set up of the PMIC RPM regulators for this board
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
2016-10-18 7:25 [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard Linus Walleij
@ 2016-10-19 0:52 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2016-10-19 0:52 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-arm-kernel, linux-arm-msm, Andy Gross, Bjorn Andersson,
David Brown
On 10/18, Linus Walleij wrote:
> @@ -167,6 +190,41 @@
> bias-pull-up;
> };
> };
> +
> + dragon_ebi2_pins: ebi2 {
> + /*
> + * Pins used by EBI2 on the Dragonboard, actually only
> + * only CS2 is used by a real peripheral. CS0 is just
> + * routed to a test point.
> + */
> + mux0 {
> + /*
> + * Pins used by EBI2 on the Dragonboard, actually only
> + * only CS2 is used by a real peripheral. CS0 is just
> + * routed to a test point.
> + */
Same comment twice? Plus it says "only only CS2", so we probably
want to drop one "only".
> + pins =
> + /* "gpio39", CS1A_N this is not good to mux */
> + "gpio40", /* CS2A_N */
> + "gpio134"; /* CS0_N testpoint TP29 */
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-10-19 0:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-10-18 7:25 [PATCH 2/2] ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard Linus Walleij
2016-10-19 0:52 ` Stephen Boyd
-- strict thread matches above, loose matches on Subject: below --
2016-09-08 13:41 Linus Walleij
2016-09-08 13:52 ` Arnd Bergmann
2016-09-08 14:03 ` Linus Walleij
2016-09-08 14:32 ` Arnd Bergmann
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).