From: Stephen Boyd <sboyd@codeaurora.org>
To: Ritesh Harjani <riteshh@codeaurora.org>
Cc: adrian.hunter@intel.com, ulf.hansson@linaro.org,
linux-mmc@vger.kernel.org, shawn.lin@rock-chips.com,
andy.gross@linaro.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, david.brown@linaro.org,
linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org,
alex.lemberg@sandisk.com, mateusz.nowak@intel.com,
Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org,
kdorfman@codeaurora.org, david.griego@linaro.org,
stummala@codeaurora.org, venkatg@codeaurora.org,
rnayak@codeaurora.org, pramod.gurav@linaro.org
Subject: Re: [PATCH v7 08/14] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
Date: Tue, 15 Nov 2016 11:27:27 -0800 [thread overview]
Message-ID: <20161115192727.GD25626@codeaurora.org> (raw)
In-Reply-To: <3c1a7c72-0ac1-8ed0-87fc-238331f0645b@codeaurora.org>
On 11/15, Ritesh Harjani wrote:
> On 11/15/2016 1:07 AM, Stephen Boyd wrote:
> >On 11/14, Ritesh Harjani wrote:
> >
> >>+}
> >>+
> >>+/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
> >>+static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
> >>+{
> >>+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> >>+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> >>+ int rc;
> >>+
> >>+ if (!clock) {
> >>+ msm_host->clk_rate = clock;
> >>+ goto out;
> >>+ }
> >>+
> >>+ spin_unlock_irq(&host->lock);
> >>+ if (clock != msm_host->clk_rate) {
> >
> >Why do we need to check here? Can't we call clk_set_rate()
> >Unconditionally?
> Since it may so happen that above layers may call for ->set_clock
> function with same requested clock more than once, hence we cache
> the host->clock here.
> Also, since requested clock (host->clock) can be say 400Mhz but the
> actual pltfm supported clock would be say 384MHz.
clk_set_rate() detects the same rate being set even after it
internally rounds the rate. We're not going to touch the clk
hardware if 400 is requested once but 384 is what's set and then
400 is requested again. Caching the rate here in the driver can
lead to problems too if the driver is out of sync with the clk
hardware state, so it's best to avoid doing anything fancy here
and just let the framework handle duplicates.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-11-15 19:27 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-14 6:00 [PATCH v7 00/14] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 02/14] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops Ritesh Harjani
2016-11-15 0:06 ` Jeremy McNicoll
2016-11-14 6:00 ` [PATCH v7 03/14] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 04/14] ARM: dts: Add xo_clock to sdhc nodes on qcom platforms Ritesh Harjani
2016-11-14 20:01 ` Stephen Boyd
[not found] ` <20161114200115.GL5177-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-15 5:10 ` Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 05/14] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 06/14] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 08/14] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
2016-11-14 19:37 ` Stephen Boyd
2016-11-15 5:10 ` Ritesh Harjani
2016-11-15 19:27 ` Stephen Boyd [this message]
2016-11-16 4:42 ` Ritesh Harjani
2016-11-16 7:42 ` Adrian Hunter
2016-11-16 8:53 ` Ritesh Harjani
[not found] ` <1479103248-9491-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-14 6:00 ` [PATCH v7 01/14] clk: qcom: Add rcg ops to return floor value closest to the requested rate Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 07/14] mmc: sdhci-msm: Enable few quirks Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 09/14] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 10/14] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 11/14] mmc: sdhci-msm: Add HS400 platform support Ritesh Harjani
[not found] ` <1479103248-9491-12-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-14 13:53 ` kbuild test robot
2016-11-14 15:44 ` Ulf Hansson
[not found] ` <CAPDyKFoUiGgXhLtW9-+iAxdV6sy4+wgQfW8P5+VwsqHc3QwkqA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-11-15 0:53 ` Fengguang Wu
2016-11-14 6:00 ` [PATCH v7 12/14] mmc: sdhci-msm: Save the calculated tuning phase Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 13/14] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit Ritesh Harjani
2016-11-14 19:59 ` Stephen Boyd
2016-11-15 4:24 ` Ritesh Harjani
2016-11-14 6:00 ` [PATCH v7 14/14] sdhci: sdhci-msm: update dll configuration Ritesh Harjani
2016-11-14 19:57 ` Stephen Boyd
2016-11-15 4:23 ` Ritesh Harjani
2016-11-15 0:06 ` [PATCH v7 00/14] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Jeremy McNicoll
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