[PATCH v4 00/10]remoteproc: qcom: Add support to hexagon q6v56 in qcom hexagon rproc driver

[PATCH v4 00/10]remoteproc: qcom: Add support to hexagon q6v56 in qcom hexagon rproc driver

[Avaneesh Kumar Dwivedi]

This is patchset v4 having modifications as per comment on patchset v3.
Major changes w.r.t. patchset v3 are as below.
	1- clean up of resource struct initialization.
	2- breaking up all changes into more number of logical patches.
	3- handling of clock through array of clock pointers.
	4- single place handling of proxy and active regulators.
	5- Addressing Other comments on last patches.
	
There were certain comments which could not be addressed 
	1- To program MSS_RESET via GCC reset controller
	Since MSS_RESET does not control any clock as are done by other BCR or block control
	registers, so it does not qualify to be controlled by GCC reset controller.
	This is moreover like any other register, which can be programmed by IOREMAP.
	
This patchset is verified on top of kernel 4.9.rc4.
below is console o/p
[    3.304426]  remoteproc1: powering up 2080000.qcom,mss
[    3.304435]  remoteproc1: Booting fw image mba.mbn, size 213888
[    4.518946]  remoteproc1: remote processor 2080000.qcom,mss is now up

Avaneesh Kumar Dwivedi (10):
  remoteproc: qcom: Add and initialize private data for hexagon dsp.
  remoteproc: qcom: Initialize MSS reset control handle
  remoteproc: qcom: Initialize clock and regulator handle with private
    data
  remoteproc: qcom: Modify regulator enable and disable interface
  remoteproc: qcom: Separate out regulator disable routine in two
  remoteproc: qcom: Modify clock enable and disable routine
  remoteproc: qcom: Add new routine for mss restart programming
  remoteproc: qcom: Modify reset sequence for hexagon to support q6v56
  remoteproc: qcom: Modify stop routine for q6v56 specific step
  remoteproc: qcom: Adding required initialization for q6v5 hexagon

 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |   5 +
 drivers/remoteproc/qcom_q6v5_pil.c                 | 622 +++++++++++++++++----
 2 files changed, 504 insertions(+), 123 deletions(-)

-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 01/10] remoteproc: qcom: Add and initialize private data for hexagon dsp.

[Avaneesh Kumar Dwivedi]

Embed resources specific to version of hexagon chip in device
structure to avoid conditional check for manipulation of those
resources in driver code.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |  1 +
 drivers/remoteproc/qcom_q6v5_pil.c                 | 48 +++++++++++++++++++++-
 2 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 57cb49e..cbc165c 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -8,6 +8,7 @@ on the Qualcomm Hexagon core.
 	Value type: <string>
 	Definition: must be one of:
 		    "qcom,q6v5-pil"
+		"qcom,q6v56-pil"
 
 - reg:
 	Usage: required
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 2e0caaa..7660012 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -30,13 +30,14 @@
 #include <linux/reset.h>
 #include <linux/soc/qcom/smem.h>
 #include <linux/soc/qcom/smem_state.h>
+#include <linux/of_device.h>
 
 #include "remoteproc_internal.h"
 #include "qcom_mdt_loader.h"
 
 #include <linux/qcom_scm.h>
 
-#define MBA_FIRMWARE_NAME		"mba.b00"
+#define MBA_FIRMWARE_NAME              "mba.b00"
 #define MPSS_FIRMWARE_NAME		"modem.mdt"
 
 #define MPSS_CRASH_REASON_SMEM		421
@@ -93,6 +94,23 @@
 #define QDSS_BHS_ON			BIT(21)
 #define QDSS_LDO_BYP			BIT(22)
 
+struct q6_rproc_res {
+	char *q6_mba_image;
+	int (*q6_reset_init)(void *q, void *p);
+	char **proxy_reg_string;
+	char **active_reg_string;
+	int **proxy_voltage_load;
+	int **active_voltage_load;
+	char **proxy_clk_string;
+	char **active_clk_string;
+};
+
+struct reg_info {
+	struct regulator *reg;
+	int uV;
+	int uA;
+};
+
 struct q6v5 {
 	struct device *dev;
 	struct rproc *rproc;
@@ -890,8 +908,34 @@ static int q6v5_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static char *proxy_q6v56_regulator_namestr[] = {"mx", "cx", "pll", NULL};
+static int proxy_q6v56_voltage_load[3][2] = { {1050000, 0}, {0, 100000},
+		{0, 100000} };
+static char *proxy_q6v56_clk_namestr[] = {"xo", "pnoc", "qdss", NULL};
+static char *active_q6v56_clk_namestr[] = {"iface", "bus", "mem",
+		"gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", NULL};
+
+static const struct q6_rproc_res q6v56_res = {
+	.q6_reset_init = NULL,
+	.q6_mba_image = "mba.mbn",
+	.proxy_reg_string = proxy_q6v56_regulator_namestr,
+	.active_reg_string = NULL,
+	.proxy_voltage_load = (int **)proxy_q6v56_voltage_load,
+	.active_voltage_load = NULL,
+	.proxy_clk_string = proxy_q6v56_clk_namestr,
+	.active_clk_string = active_q6v56_clk_namestr,
+};
+
+static const struct q6_rproc_res q6v5_res = {
+	.q6_reset_init = NULL,
+	.q6_mba_image = "mba.mbn",
+	.proxy_reg_string = proxy_q6v56_regulator_namestr,
+	.proxy_voltage_load = (int **)proxy_q6v56_voltage_load,
+};
+
 static const struct of_device_id q6v5_of_match[] = {
-	{ .compatible = "qcom,q6v5-pil", },
+	{ .compatible = "qcom,q6v5-pil", .data = &q6v5_res},
+	{ .compatible = "qcom,q6v56-pil", .data = &q6v56_res},
 	{ },
 };
 
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 02/10] remoteproc: qcom: Initialize MSS reset control handle

[Avaneesh Kumar Dwivedi]

Reset assert of mss need to be done before mss clocks are
enabled and hexagon starts ticking. On some platform handle
to program restart register is via reset control framework
while on some it is by direct ioremap.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 40 ++++++++++++++++++++++++++++++--------
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 7660012..f43c96b 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -37,7 +37,6 @@
 
 #include <linux/qcom_scm.h>
 
-#define MBA_FIRMWARE_NAME              "mba.b00"
 #define MPSS_FIRMWARE_NAME		"modem.mdt"
 
 #define MPSS_CRASH_REASON_SMEM		421
@@ -117,7 +116,7 @@ struct q6v5 {
 
 	void __iomem *reg_base;
 	void __iomem *rmb_base;
-
+	void __iomem *restart_reg;
 	struct regmap *halt_map;
 	u32 halt_q6;
 	u32 halt_modem;
@@ -743,9 +742,12 @@ static int q6v5_init_clocks(struct q6v5 *qproc)
 	return 0;
 }
 
-static int q6v5_init_reset(struct q6v5 *qproc)
+static int q6v5_init_reset(void *q, void *p)
 {
-	qproc->mss_restart = devm_reset_control_get(qproc->dev, NULL);
+	struct q6v5 *qproc = q;
+	struct platform_device *pdev = p;
+
+	qproc->mss_restart = devm_reset_control_get(&pdev->dev, NULL);
 	if (IS_ERR(qproc->mss_restart)) {
 		dev_err(qproc->dev, "failed to acquire mss restart\n");
 		return PTR_ERR(qproc->mss_restart);
@@ -754,6 +756,23 @@ static int q6v5_init_reset(struct q6v5 *qproc)
 	return 0;
 }
 
+static int q6v56_init_reset(void *q, void *p)
+{
+	struct resource *res;
+	struct q6v5 *qproc = q;
+	struct platform_device *pdev = p;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "restart_reg");
+	qproc->restart_reg = devm_ioremap(qproc->dev, res->start,
+							resource_size(res));
+	if (IS_ERR(qproc->restart_reg)) {
+		dev_err(qproc->dev, "failed to get restart_reg\n");
+		return PTR_ERR(qproc->restart_reg);
+	}
+
+	return 0;
+}
+
 static int q6v5_request_irq(struct q6v5 *qproc,
 			     struct platform_device *pdev,
 			     const char *name,
@@ -825,10 +844,15 @@ static int q6v5_probe(struct platform_device *pdev)
 {
 	struct q6v5 *qproc;
 	struct rproc *rproc;
+	const struct q6_rproc_res *desc;
 	int ret;
 
+	desc = of_device_get_match_data(&pdev->dev);
+	if (!desc)
+		return -EINVAL;
+
 	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
-			    MBA_FIRMWARE_NAME, sizeof(*qproc));
+			    desc->q6_mba_image, sizeof(*qproc));
 	if (!rproc) {
 		dev_err(&pdev->dev, "failed to allocate rproc\n");
 		return -ENOMEM;
@@ -860,7 +884,7 @@ static int q6v5_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_rproc;
 
-	ret = q6v5_init_reset(qproc);
+	ret = desc->q6_reset_init(qproc, pdev);
 	if (ret)
 		goto free_rproc;
 
@@ -916,7 +940,7 @@ static int q6v5_remove(struct platform_device *pdev)
 		"gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", NULL};
 
 static const struct q6_rproc_res q6v56_res = {
-	.q6_reset_init = NULL,
+	.q6_reset_init = q6v56_init_reset,
 	.q6_mba_image = "mba.mbn",
 	.proxy_reg_string = proxy_q6v56_regulator_namestr,
 	.active_reg_string = NULL,
@@ -927,7 +951,7 @@ static int q6v5_remove(struct platform_device *pdev)
 };
 
 static const struct q6_rproc_res q6v5_res = {
-	.q6_reset_init = NULL,
+	.q6_reset_init = q6v5_init_reset,
 	.q6_mba_image = "mba.mbn",
 	.proxy_reg_string = proxy_q6v56_regulator_namestr,
 	.proxy_voltage_load = (int **)proxy_q6v56_voltage_load,
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 03/10] remoteproc: qcom: Initialize clock and regulator handle with private data

[Avaneesh Kumar Dwivedi]

Clock and voltage regulator voting is needed before we take hexagon
out of reset. Certain regulators and clocks need voting by rproc on
behalf of hexagon only during restart operation but certain clocks
and voltage need to be voted till hexagon is up, these regulators
and clocks are identified as proxy and active resource whose handle is
being obtained by supplying private proxy and active regulator and clock
string.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 148 +++++++++++++++++++++++++++----------
 1 file changed, 109 insertions(+), 39 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index f43c96b..32e4bbc 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -132,6 +132,14 @@ struct q6v5 {
 	struct clk *ahb_clk;
 	struct clk *axi_clk;
 	struct clk *rom_clk;
+	struct clk **active_clks;
+	struct clk **proxy_clks;
+	struct reg_info *active_regs;
+	struct reg_info *proxy_regs;
+	int active_reg_count;
+	int proxy_reg_count;
+	int active_clk_count;
+	int proxy_clk_count;
 
 	struct completion start_done;
 	struct completion stop_done;
@@ -154,27 +162,48 @@ enum {
 	Q6V5_SUPPLY_PLL,
 };
 
-static int q6v5_regulator_init(struct q6v5 *qproc)
+static int q6v5_regulator_init(struct device *dev,
+	struct reg_info **regs_ref, char **reg_str, int volatage_load[][2])
 {
-	int ret;
+	int reg_count = 0, i;
+	struct reg_info *regs;
 
-	qproc->supply[Q6V5_SUPPLY_CX].supply = "cx";
-	qproc->supply[Q6V5_SUPPLY_MX].supply = "mx";
-	qproc->supply[Q6V5_SUPPLY_MSS].supply = "mss";
-	qproc->supply[Q6V5_SUPPLY_PLL].supply = "pll";
+	if (!reg_str)
+		return 0;
 
-	ret = devm_regulator_bulk_get(qproc->dev,
-				      ARRAY_SIZE(qproc->supply), qproc->supply);
-	if (ret < 0) {
-		dev_err(qproc->dev, "failed to get supplies\n");
-		return ret;
-	}
+	while (reg_str[reg_count] != NULL)
+		reg_count++;
 
-	regulator_set_load(qproc->supply[Q6V5_SUPPLY_CX].consumer, 100000);
-	regulator_set_load(qproc->supply[Q6V5_SUPPLY_MSS].consumer, 100000);
-	regulator_set_load(qproc->supply[Q6V5_SUPPLY_PLL].consumer, 10000);
+	if (!reg_count)
+		return reg_count;
 
-	return 0;
+	regs = devm_kzalloc(dev, sizeof(struct reg_info) * reg_count,
+				GFP_KERNEL);
+
+	if (!regs)
+		return -ENOMEM;
+
+	for (i = 0; i < reg_count; i++) {
+		const char *reg_name;
+
+		reg_name = reg_str[i];
+		regs[i].reg = devm_regulator_get(dev, reg_name);
+		if (IS_ERR(regs[i].reg)) {
+
+			int rc = PTR_ERR(regs[i].reg);
+
+			if (rc != -EPROBE_DEFER)
+				dev_err(dev, "Failed to get %s\n regulator",
+								reg_name);
+			return rc;
+		}
+
+		regs[i].uV = volatage_load[i][0];
+		regs[i].uA = volatage_load[i][1];
+	}
+
+	*regs_ref = regs;
+	return reg_count;
 }
 
 static int q6v5_regulator_enable(struct q6v5 *qproc)
@@ -719,27 +748,45 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
 	return 0;
 }
 
-static int q6v5_init_clocks(struct q6v5 *qproc)
+static int q6v5_init_clocks(struct device *dev, struct clk ***clks_ref,
+		char **clk_str)
 {
-	qproc->ahb_clk = devm_clk_get(qproc->dev, "iface");
-	if (IS_ERR(qproc->ahb_clk)) {
-		dev_err(qproc->dev, "failed to get iface clock\n");
-		return PTR_ERR(qproc->ahb_clk);
-	}
+	int clk_count = 0, i;
+	struct clk **clks;
 
-	qproc->axi_clk = devm_clk_get(qproc->dev, "bus");
-	if (IS_ERR(qproc->axi_clk)) {
-		dev_err(qproc->dev, "failed to get bus clock\n");
-		return PTR_ERR(qproc->axi_clk);
-	}
+	if (!clk_str)
+		return 0;
+
+	while (clk_str[clk_count] != NULL)
+		clk_count++;
+
+	if (!clk_count)
+		return clk_count;
+
+	clks = devm_kzalloc(dev, sizeof(struct clk *) * clk_count,
+				GFP_KERNEL);
+	if (!clks)
+		return -ENOMEM;
+
+	for (i = 0; i < clk_count; i++) {
+		const char *clock_name;
+
+		clock_name = clk_str[i];
+		clks[i] = devm_clk_get(dev, clock_name);
+		if (IS_ERR(clks[i])) {
+
+			int rc = PTR_ERR(clks[i]);
+
+			if (rc != -EPROBE_DEFER)
+				dev_err(dev, "Failed to get %s clock\n",
+					clock_name);
+			return rc;
+		}
 
-	qproc->rom_clk = devm_clk_get(qproc->dev, "mem");
-	if (IS_ERR(qproc->rom_clk)) {
-		dev_err(qproc->dev, "failed to get mem clock\n");
-		return PTR_ERR(qproc->rom_clk);
 	}
 
-	return 0;
+	*clks_ref = clks;
+	return clk_count;
 }
 
 static int q6v5_init_reset(void *q, void *p)
@@ -845,7 +892,7 @@ static int q6v5_probe(struct platform_device *pdev)
 	struct q6v5 *qproc;
 	struct rproc *rproc;
 	const struct q6_rproc_res *desc;
-	int ret;
+	int ret, count;
 
 	desc = of_device_get_match_data(&pdev->dev);
 	if (!desc)
@@ -876,17 +923,40 @@ static int q6v5_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_rproc;
 
-	ret = q6v5_init_clocks(qproc);
-	if (ret)
-		goto free_rproc;
+	count = q6v5_init_clocks(&pdev->dev, &qproc->proxy_clks,
+		desc->proxy_clk_string);
+	if (count < 0) {
+		dev_err(&pdev->dev, "Failed to setup proxy clocks.\n");
+		return count;
+	}
+	qproc->proxy_clk_count = count;
 
-	ret = q6v5_regulator_init(qproc);
-	if (ret)
-		goto free_rproc;
+	count = q6v5_init_clocks(&pdev->dev, &qproc->active_clks,
+		desc->active_clk_string);
+	if (count < 0) {
+		dev_err(&pdev->dev, "Failed to setup active clocks.\n");
+		return count;
+	}
+	qproc->active_clk_count = count;
 
 	ret = desc->q6_reset_init(qproc, pdev);
 	if (ret)
 		goto free_rproc;
+	count = q6v5_regulator_init(&pdev->dev, &qproc->proxy_regs,
+		desc->proxy_reg_string, (int (*)[2])desc->proxy_voltage_load);
+	if (count < 0) {
+		dev_err(&pdev->dev, "Failed to setup active regulators.\n");
+		return count;
+	}
+	qproc->proxy_reg_count = count;
+
+	count = q6v5_regulator_init(&pdev->dev, &qproc->active_regs,
+		desc->active_reg_string, (int (*)[2])desc->active_voltage_load);
+	if (count < 0) {
+		dev_err(&pdev->dev, "Failed to setup proxy regulators.\n");
+		return count;
+	}
+	qproc->active_reg_count = count;
 
 	ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
 	if (ret < 0)
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 04/10] remoteproc: qcom: Modify regulator enable and disable interface

[Avaneesh Kumar Dwivedi]

Regulator enable routine will get additional input parameter of
regulator info and count, It will read regulator info and will do
appropriate voltage and load configuration before turning them up.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 87 ++++++++++++++++++++++++++------------
 1 file changed, 59 insertions(+), 28 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 32e4bbc..8843605 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -127,7 +127,6 @@ struct q6v5 {
 	struct qcom_smem_state *state;
 	unsigned stop_bit;
 
-	struct regulator_bulk_data supply[4];
 
 	struct clk *ahb_clk;
 	struct clk *axi_clk;
@@ -155,12 +154,6 @@ struct q6v5 {
 	size_t mpss_size;
 };
 
-enum {
-	Q6V5_SUPPLY_CX,
-	Q6V5_SUPPLY_MX,
-	Q6V5_SUPPLY_MSS,
-	Q6V5_SUPPLY_PLL,
-};
 
 static int q6v5_regulator_init(struct device *dev,
 	struct reg_info **regs_ref, char **reg_str, int volatage_load[][2])
@@ -206,33 +199,64 @@ static int q6v5_regulator_init(struct device *dev,
 	return reg_count;
 }
 
-static int q6v5_regulator_enable(struct q6v5 *qproc)
+static int q6v5_regulator_enable(struct q6v5 *qproc,
+	struct reg_info *regs, int count)
 {
-	struct regulator *mss = qproc->supply[Q6V5_SUPPLY_MSS].consumer;
-	struct regulator *mx = qproc->supply[Q6V5_SUPPLY_MX].consumer;
-	int ret;
+	int i, rc = 0;
+
+	for (i = 0; i < count; i++) {
+		if (regs[i].uV > 0) {
+			rc = regulator_set_voltage(regs[i].reg,
+					regs[i].uV, INT_MAX);
+			if (rc) {
+				dev_err(qproc->dev,
+					"Failed to request voltage for %d.\n",
+						i);
+				goto err_voltage;
+			}
+		}
 
-	/* TODO: Q6V5_SUPPLY_CX is supposed to be set to super-turbo here */
+		if (regs[i].uA > 0) {
+			rc = regulator_set_load(regs[i].reg,
+						regs[i].uA);
+			if (rc < 0) {
+				dev_err(qproc->dev, "Failed to set regulator mode\n");
+				goto err_load;
+			}
+		}
 
-	ret = regulator_set_voltage(mx, 1050000, INT_MAX);
-	if (ret)
-		return ret;
+		rc = regulator_enable(regs[i].reg);
+		if (rc) {
+			dev_err(qproc->dev, "Regulator enable failed\n");
+			goto err_enable;
+		}
+	}
 
-	regulator_set_voltage(mss, 1000000, 1150000);
+	return 0;
+err_enable:
+	if (regs[i].uA > 0) {
+		regulator_set_voltage(regs[i].reg, 0, INT_MAX);
+		regulator_set_load(regs[i].reg, 0);
+	}
+err_load:
+	if (regs[i].uV > 0)
+		regulator_set_voltage(regs[i].reg, 0, INT_MAX);
+err_voltage:
+	for (i--; i >= 0; i--) {
+		if (regs[i].uV > 0)
+			regulator_set_voltage(regs[i].reg, 0, INT_MAX);
+
+		if (regs[i].uA > 0)
+			regulator_set_load(regs[i].reg, 0);
+
+		regulator_disable(regs[i].reg);
+	}
 
-	return regulator_bulk_enable(ARRAY_SIZE(qproc->supply), qproc->supply);
+	return rc;
 }
 
 static void q6v5_regulator_disable(struct q6v5 *qproc)
 {
-	struct regulator *mss = qproc->supply[Q6V5_SUPPLY_MSS].consumer;
-	struct regulator *mx = qproc->supply[Q6V5_SUPPLY_MX].consumer;
-
-	/* TODO: Q6V5_SUPPLY_CX corner votes should be released */
-
-	regulator_bulk_disable(ARRAY_SIZE(qproc->supply), qproc->supply);
-	regulator_set_voltage(mx, 0, INT_MAX);
-	regulator_set_voltage(mss, 0, 1150000);
 }
 
 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
@@ -524,12 +548,19 @@ static int q6v5_start(struct rproc *rproc)
 	struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
 	int ret;
 
-	ret = q6v5_regulator_enable(qproc);
+	ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
+		qproc->proxy_reg_count);
 	if (ret) {
-		dev_err(qproc->dev, "failed to enable supplies\n");
+		dev_err(qproc->dev, "failed to enable proxy supplies\n");
 		return ret;
 	}
 
+	ret = q6v5_regulator_enable(qproc, qproc->active_regs,
+		qproc->active_reg_count);
+	if (ret) {
+		dev_err(qproc->dev, "failed to enable supplies\n");
+		goto disable_proxy_clk;
+	}
 	ret = reset_control_deassert(qproc->mss_restart);
 	if (ret) {
 		dev_err(qproc->dev, "failed to deassert mss restart\n");
@@ -599,7 +630,7 @@ static int q6v5_start(struct rproc *rproc)
 	reset_control_assert(qproc->mss_restart);
 disable_vdd:
 	q6v5_regulator_disable(qproc);
-
+disable_proxy_clk:
 	return ret;
 }
 
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 05/10] remoteproc: qcom: Separate out regulator disable routine in two

[Avaneesh Kumar Dwivedi]

It is needed that one disable proxy regulators when handover interrupt
is received from mss subsystem while on certain chip there are few
regulator which are never disabled. So separating out disable interface
in two separate routine.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 36 +++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 8843605..57c67e1 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -255,8 +255,42 @@ static int q6v5_regulator_enable(struct q6v5 *qproc,
 	return rc;
 }
 
+static void q6v5_proxy_regulator_disable(struct q6v5 *qproc)
+{
+	int i;
+	struct reg_info *regs = qproc->proxy_regs;
+
+	for (i = 0; i < qproc->proxy_reg_count; i++) {
+		if (regs[i].uV > 0)
+			regulator_set_voltage(regs[i].reg, 0, INT_MAX);
+
+		if (regs[i].uA > 0)
+			regulator_set_load(regs[i].reg, 0);
+
+		regulator_disable(regs[i].reg);
+	}
+}
+
+static void q6v5_active_regulator_disable(struct q6v5 *qproc)
+{
+	int i;
+	struct reg_info *regs = qproc->active_regs;
+
+	for (i = 0; i < qproc->active_reg_count; i++) {
+		if (regs[i].uV > 0)
+			regulator_set_voltage(regs[i].reg, 0, INT_MAX);
+
+		if (regs[i].uA > 0)
+			regulator_set_load(regs[i].reg, 0);
+
+		regulator_disable(regs[i].reg);
+	}
+}
+
 static void q6v5_regulator_disable(struct q6v5 *qproc)
 {
+	q6v5_proxy_regulator_disable(qproc);
+	q6v5_active_regulator_disable(qproc);
 }
 
 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
@@ -629,7 +663,7 @@ static int q6v5_start(struct rproc *rproc)
 assert_reset:
 	reset_control_assert(qproc->mss_restart);
 disable_vdd:
-	q6v5_regulator_disable(qproc);
+	q6v5_active_regulator_disable(qproc);
 disable_proxy_clk:
 	return ret;
 }
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 06/10] remoteproc: qcom: Modify clock enable and disable routine

[Avaneesh Kumar Dwivedi]

Clock handling is made generic than need to add new clock
every time when required to support new hexagon version.
also where ever required invoking clock enable disable
routine is replaced by this new prototype. Also clock disable
interface is separated out into two separate routine to handle
proxy clock alone unvoting when handover interrupt is arrived.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 90 +++++++++++++++++++++++++++-----------
 1 file changed, 65 insertions(+), 25 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 57c67e1..fe7c409 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -127,10 +127,6 @@ struct q6v5 {
 	struct qcom_smem_state *state;
 	unsigned stop_bit;
 
-
-	struct clk *ahb_clk;
-	struct clk *axi_clk;
-	struct clk *rom_clk;
 	struct clk **active_clks;
 	struct clk **proxy_clks;
 	struct reg_info *active_regs;
@@ -293,6 +289,52 @@ static void q6v5_regulator_disable(struct q6v5 *qproc)
 	q6v5_active_regulator_disable(qproc);
 }
 
+static int q6v5_clk_enable(struct device *dev, struct clk **clks,
+								int clk_count)
+{
+	int rc = 0;
+	int i;
+
+	for (i = 0; i < clk_count; i++) {
+		rc = clk_prepare_enable(clks[i]);
+		if (rc) {
+			dev_err(dev, "Clock enable failed\n");
+			goto err;
+		}
+	}
+
+	return 0;
+err:
+	for (i--; i >= 0; i--)
+		clk_disable_unprepare(clks[i]);
+
+	return rc;
+}
+
+static void q6v5_proxy_clk_disable(struct q6v5 *qproc)
+{
+	int i;
+	struct clk **clks = qproc->proxy_clks;
+
+	for (i = 0; i < qproc->proxy_clk_count; i++)
+		clk_disable_unprepare(clks[i]);
+}
+
+static void q6v5_active_clk_disable(struct q6v5 *qproc)
+{
+	int i;
+	struct clk **clks = qproc->proxy_clks;
+
+	for (i = 0; i < qproc->proxy_clk_count; i++)
+		clk_disable_unprepare(clks[i]);
+}
+
+static void q6v5_clk_disable(struct q6v5 *qproc)
+{
+	q6v5_proxy_clk_disable(qproc);
+	q6v5_active_clk_disable(qproc);
+}
+
 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 {
 	struct q6v5 *qproc = rproc->priv;
@@ -589,6 +631,13 @@ static int q6v5_start(struct rproc *rproc)
 		return ret;
 	}
 
+	ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
+		qproc->proxy_clk_count);
+	if (ret) {
+		dev_err(qproc->dev, "failed to enable proxy clocks\n");
+		goto disable_proxy_reg;
+	}
+
 	ret = q6v5_regulator_enable(qproc, qproc->active_regs,
 		qproc->active_reg_count);
 	if (ret) {
@@ -601,17 +650,12 @@ static int q6v5_start(struct rproc *rproc)
 		goto disable_vdd;
 	}
 
-	ret = clk_prepare_enable(qproc->ahb_clk);
-	if (ret)
+	ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
+		qproc->active_clk_count);
+	if (ret) {
+		dev_err(qproc->dev, "failed to enable clocks\n");
 		goto assert_reset;
-
-	ret = clk_prepare_enable(qproc->axi_clk);
-	if (ret)
-		goto disable_ahb_clk;
-
-	ret = clk_prepare_enable(qproc->rom_clk);
-	if (ret)
-		goto disable_axi_clk;
+	}
 
 	writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
 
@@ -646,25 +690,23 @@ static int q6v5_start(struct rproc *rproc)
 
 	qproc->running = true;
 
-	/* TODO: All done, release the handover resources */
-
+	q6v5_proxy_clk_disable(qproc);
+	q6v5_proxy_regulator_disable(qproc);
 	return 0;
 
 halt_axi_ports:
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
-
-	clk_disable_unprepare(qproc->rom_clk);
-disable_axi_clk:
-	clk_disable_unprepare(qproc->axi_clk);
-disable_ahb_clk:
-	clk_disable_unprepare(qproc->ahb_clk);
+	q6v5_active_clk_disable(qproc);
 assert_reset:
 	reset_control_assert(qproc->mss_restart);
 disable_vdd:
 	q6v5_active_regulator_disable(qproc);
 disable_proxy_clk:
+	q6v5_proxy_clk_disable(qproc);
+disable_proxy_reg:
+	q6v5_proxy_regulator_disable(qproc);
 	return ret;
 }
 
@@ -690,9 +732,7 @@ static int q6v5_stop(struct rproc *rproc)
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 
 	reset_control_assert(qproc->mss_restart);
-	clk_disable_unprepare(qproc->rom_clk);
-	clk_disable_unprepare(qproc->axi_clk);
-	clk_disable_unprepare(qproc->ahb_clk);
+	q6v5_clk_disable(qproc);
 	q6v5_regulator_disable(qproc);
 
 	return 0;
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 07/10] remoteproc: qcom: Add new routine for mss restart programming

[Avaneesh Kumar Dwivedi]

MSS restart is done via reset controller, but on certain hexagon
version clock reset controller interface can not be utilized as
MSS restart register is not a block control reset which are
supported via clock reset control framework. In this case
restart register is programmed directly by register programming
through ioremap.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |  4 +++
 drivers/remoteproc/qcom_q6v5_pil.c                 | 35 ++++++++++++++++++----
 2 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index cbc165c..717bd4a 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -79,6 +79,10 @@ on the Qualcomm Hexagon core.
 	Definition: a phandle reference to a syscon representing TCSR followed
 		    by the three offsets within syscon for q6, modem and nc
 		    halt registers.
+- qcom,qdsp6v56-1-5:
+	Usage: required
+	Value type: boolean
+	Definition: Present if the qdsp version is v56 1.5
 
 = SUBNODES:
 The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index fe7c409..77a69eb 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -148,6 +148,8 @@ struct q6v5 {
 	phys_addr_t mpss_reloc;
 	void *mpss_region;
 	size_t mpss_size;
+
+	bool qdsp6v56_1_5;
 };
 
 
@@ -335,6 +337,14 @@ static void q6v5_clk_disable(struct q6v5 *qproc)
 	q6v5_active_clk_disable(qproc);
 }
 
+static void pil_mss_restart_reg(struct q6v5 *qproc, u32 mss_restart)
+{
+	if (qproc->restart_reg) {
+		writel_relaxed(mss_restart, qproc->restart_reg);
+		udelay(2);
+	}
+}
+
 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 {
 	struct q6v5 *qproc = rproc->priv;
@@ -644,10 +654,15 @@ static int q6v5_start(struct rproc *rproc)
 		dev_err(qproc->dev, "failed to enable supplies\n");
 		goto disable_proxy_clk;
 	}
-	ret = reset_control_deassert(qproc->mss_restart);
-	if (ret) {
-		dev_err(qproc->dev, "failed to deassert mss restart\n");
+
+	if (qproc->qdsp6v56_1_5)
+		pil_mss_restart_reg(qproc, 0);
+	else {
+		ret = reset_control_deassert(qproc->mss_restart);
+		if (ret) {
+			dev_err(qproc->dev, "failed to deassert mss restart\n");
 		goto disable_vdd;
+		}
 	}
 
 	ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
@@ -700,7 +715,8 @@ static int q6v5_start(struct rproc *rproc)
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 	q6v5_active_clk_disable(qproc);
 assert_reset:
-	reset_control_assert(qproc->mss_restart);
+	if (qproc->qdsp6v56_1_5)
+		reset_control_assert(qproc->mss_restart);
 disable_vdd:
 	q6v5_active_regulator_disable(qproc);
 disable_proxy_clk:
@@ -731,7 +747,13 @@ static int q6v5_stop(struct rproc *rproc)
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 
-	reset_control_assert(qproc->mss_restart);
+	if (qproc->qdsp6v56_1_5)
+		pil_mss_restart_reg(qproc, 1);
+	else {
+		ret = reset_control_assert(qproc->mss_restart);
+		if (ret)
+			dev_err(qproc->dev, "failed to deassert mss restart\n");
+	}
 	q6v5_clk_disable(qproc);
 	q6v5_regulator_disable(qproc);
 
@@ -1063,6 +1085,9 @@ static int q6v5_probe(struct platform_device *pdev)
 	}
 	qproc->active_reg_count = count;
 
+	qproc->qdsp6v56_1_5 = of_property_read_bool(pdev->dev.of_node,
+						"qcom,qdsp6v56-1-5");
+
 	ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
 	if (ret < 0)
 		goto free_rproc;
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 08/10] remoteproc: qcom: Modify reset sequence for hexagon to support q6v56

[Avaneesh Kumar Dwivedi]

This change introduces appropriate additional steps in reset sequence
so that hexagon on q6v56 is brough out of reset.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 126 ++++++++++++++++++++++++++++++-------
 1 file changed, 104 insertions(+), 22 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 77a69eb..3fccde4 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -65,6 +65,8 @@
 #define QDSP6SS_RESET_REG		0x014
 #define QDSP6SS_GFMUX_CTL_REG		0x020
 #define QDSP6SS_PWR_CTL_REG		0x030
+#define QDSP6SS_MEM_PWR_CTL		0x0B0
+#define QDSP6SS_STRAP_ACC		0x110
 
 /* AXI Halt Register Offsets */
 #define AXI_HALTREQ_REG			0x0
@@ -93,6 +95,15 @@
 #define QDSS_BHS_ON			BIT(21)
 #define QDSS_LDO_BYP			BIT(22)
 
+/* QDSP6v56 parameters */
+#define QDSP6v56_LDO_BYP                BIT(25)
+#define QDSP6v56_BHS_ON                 BIT(24)
+#define QDSP6v56_CLAMP_WL               BIT(21)
+#define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
+#define HALT_CHECK_MAX_LOOPS            (200)
+#define QDSP6SS_XO_CBCR                 (0x0038)
+#define QDSP6SS_ACC_OVERRIDE_VAL	0x20
+
 struct q6_rproc_res {
 	char *q6_mba_image;
 	int (*q6_reset_init)(void *q, void *p);
@@ -407,35 +418,106 @@ static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 
 static int q6v5proc_reset(struct q6v5 *qproc)
 {
-	u32 val;
-	int ret;
+	int ret, i, count;
+	u64 val;
+
+	/* Override the ACC value if required */
+	if (qproc->qdsp6v56_1_5)
+		writel_relaxed(QDSP6SS_ACC_OVERRIDE_VAL,
+				qproc->reg_base + QDSP6SS_STRAP_ACC);
 
 	/* Assert resets, stop core */
 	val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 	val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE);
 	writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 
-	/* Enable power block headswitch, and wait for it to stabilize */
-	val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-	val |= QDSS_BHS_ON | QDSS_LDO_BYP;
-	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-	udelay(1);
-
-	/*
-	 * Turn on memories. L2 banks should be done individually
-	 * to minimize inrush current.
-	 */
-	val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-	val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
-		Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
-	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-	val |= Q6SS_L2DATA_SLP_NRET_N_2;
-	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-	val |= Q6SS_L2DATA_SLP_NRET_N_1;
-	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-	val |= Q6SS_L2DATA_SLP_NRET_N_0;
-	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	/* BHS require xo cbcr to be enabled */
+	if (qproc->qdsp6v56_1_5) {
+		val = readl_relaxed(qproc->reg_base + QDSP6SS_XO_CBCR);
+		val |= 0x1;
+		writel_relaxed(val, qproc->reg_base + QDSP6SS_XO_CBCR);
+		for (count = HALT_CHECK_MAX_LOOPS; count > 0; count--) {
+			val = readl_relaxed(qproc->reg_base + QDSP6SS_XO_CBCR);
+			if (!(val & BIT(31)))
+				break;
+			udelay(1);
+		}
 
+		val = readl_relaxed(qproc->reg_base + QDSP6SS_XO_CBCR);
+		if ((val & BIT(31)))
+			dev_err(qproc->dev, "Failed to enable xo branch clock.\n");
+	}
+
+	if (qproc->qdsp6v56_1_5) {
+		/*
+		 * Enable power block headswitch,
+		 * and wait for it to stabilize
+		 */
+		val = readl_relaxed(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= QDSP6v56_BHS_ON;
+		writel_relaxed(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		udelay(1);
+
+		/* Put LDO in bypass mode */
+		val |= QDSP6v56_LDO_BYP;
+		writel_relaxed(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+	} else {
+		/*
+		 * Enable power block headswitch,
+		 * and wait for it to stabilize
+		 */
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= QDSS_BHS_ON | QDSS_LDO_BYP;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		udelay(1);
+	}
+
+	if (qproc->qdsp6v56_1_5) {
+		/*
+		 * Deassert QDSP6 compiler memory clamp
+		 */
+		val = readl_relaxed(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val &= ~QDSP6v56_CLAMP_QMC_MEM;
+		writel_relaxed(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+		/* Deassert memory peripheral sleep and L2 memory standby */
+		val |= (Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N);
+		writel_relaxed(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+		/* Turn on L1, L2, ETB and JU memories 1 at a time */
+		val = readl_relaxed(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+		for (i = 19; i >= 0; i--) {
+			val |= BIT(i);
+			writel_relaxed(val, qproc->reg_base +
+						QDSP6SS_MEM_PWR_CTL);
+			/*
+			 * Wait for 1us for both memory peripheral and
+			 * data array to turn on.
+			 */
+			 mb();
+			udelay(1);
+		}
+		/* Remove word line clamp */
+		val = readl_relaxed(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val &= ~QDSP6v56_CLAMP_WL;
+		writel_relaxed(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	} else {
+		/*
+		 * Turn on memories. L2 banks should be done individually
+		 * to minimize inrush current.
+		 */
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
+			Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= Q6SS_L2DATA_SLP_NRET_N_2;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= Q6SS_L2DATA_SLP_NRET_N_1;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= Q6SS_L2DATA_SLP_NRET_N_0;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	}
 	/* Remove IO clamp */
 	val &= ~Q6SS_CLAMP_IO;
 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 09/10] remoteproc: qcom: Modify stop routine for q6v56 specific step

[Avaneesh Kumar Dwivedi]

for q6v56 compatible mss chip, certain version of hexagon chip
require to limit high MX current during restart, so this additional
step.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 3fccde4..3135832 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -811,7 +811,7 @@ static int q6v5_start(struct rproc *rproc)
 static int q6v5_stop(struct rproc *rproc)
 {
 	struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
-	int ret;
+	int ret, val;
 
 	qproc->running = false;
 
@@ -829,6 +829,23 @@ static int q6v5_stop(struct rproc *rproc)
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 
+	if (qproc->qdsp6v56_1_5) {
+		/*
+		 * Assert QDSP6 I/O clamp, memory wordline clamp, and compiler
+		 * memory clamp as a software workaround to avoid high MX
+		 * current during LPASS/MSS restart.
+		 */
+		ret = clk_prepare_enable(devm_clk_get(qproc->dev, "iface"));
+		if (!ret) {
+			val = readl_relaxed(
+				qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+			val |= (Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
+				QDSP6v56_CLAMP_QMC_MEM);
+			writel_relaxed(val,
+				qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		}
+	}
+
 	if (qproc->qdsp6v56_1_5)
 		pil_mss_restart_reg(qproc, 1);
 	else {
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

[PATCH v4 10/10] remoteproc: qcom: Adding required initialization for q6v5 hexagon

[Avaneesh Kumar Dwivedi]

Initialization of q6v5 specific resources were missed, adding them
back. This driver supports q6v56 and q6v5.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_pil.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index 3135832..3a926e7 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -1249,11 +1249,20 @@ static int q6v5_remove(struct platform_device *pdev)
 	.active_clk_string = active_q6v56_clk_namestr,
 };
 
+static char *active_q6v5_regulator_namestr[] = {"mss", NULL};
+static int active_q6v5_voltage_load[1][2] = { {1000000, 100000} };
+static char *proxy_q6v5_clk_namestr[] = {"xo", NULL};
+static char *active_q6v5_clk_namestr[] = {"iface", "bus", "mem", NULL};
+
 static const struct q6_rproc_res q6v5_res = {
 	.q6_reset_init = q6v5_init_reset,
 	.q6_mba_image = "mba.mbn",
 	.proxy_reg_string = proxy_q6v56_regulator_namestr,
 	.proxy_voltage_load = (int **)proxy_q6v56_voltage_load,
+	.active_reg_string = active_q6v5_regulator_namestr,
+	.active_voltage_load = (int **)active_q6v5_voltage_load,
+	.proxy_clk_string = proxy_q6v5_clk_namestr,
+	.active_clk_string = active_q6v5_clk_namestr,
 };
 
 static const struct of_device_id q6v5_of_match[] = {
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH v4 00/10]remoteproc: qcom: Add support to hexagon q6v56 in qcom hexagon rproc driver

[Stephen Boyd]

On 11/16, Avaneesh Kumar Dwivedi wrote:
> This is patchset v4 having modifications as per comment on patchset v3.
> Major changes w.r.t. patchset v3 are as below.
> 	1- clean up of resource struct initialization.
> 	2- breaking up all changes into more number of logical patches.
> 	3- handling of clock through array of clock pointers.
> 	4- single place handling of proxy and active regulators.
> 	5- Addressing Other comments on last patches.
> 	
> There were certain comments which could not be addressed 
> 	1- To program MSS_RESET via GCC reset controller
> 	Since MSS_RESET does not control any clock as are done by other BCR or block control
> 	registers, so it does not qualify to be controlled by GCC reset controller.
> 	This is moreover like any other register, which can be programmed by IOREMAP.

Sorry I don't understand this reasoning at all. If MSS_RESET
lives in GCC, then it should be exposed as a reset through the
linux kernel reset APIs. It doesn't matter if that reset controls
or doesn't control a clock in the hardware implementation.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project