From: Rob Clark <robdclark@gmail.com>
To: iommu@lists.linux-foundation.org
Cc: linux-arm-msm@vger.kernel.org,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will.deacon@arm.com>,
Sricharan <sricharan@codeaurora.org>,
Mark Rutland <mark.rutland@arm.com>,
Stanimir Varbanov <stanimir.varbanov@linaro.org>,
Rob Clark <robdclark@gmail.com>
Subject: [PATCH 6/9] iommu: qcom: initialize secure page table
Date: Tue, 14 Mar 2017 11:18:08 -0400 [thread overview]
Message-ID: <20170314151811.17234-7-robdclark@gmail.com> (raw)
In-Reply-To: <20170314151811.17234-1-robdclark@gmail.com>
From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
---
drivers/iommu/qcom_iommu.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 6b7adbf..743a628 100644
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -608,6 +608,51 @@ static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
clk_disable_unprepare(qcom_iommu->iface_clk);
}
+static int qcom_iommu_sec_ptbl_init(struct device *dev)
+{
+ size_t psize = 0;
+ unsigned int spare = 0;
+ void *cpu_addr;
+ dma_addr_t paddr;
+ unsigned long attrs;
+ static bool allocated = false;
+ int ret;
+
+ if (allocated)
+ return 0;
+
+ ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
+ if (ret) {
+ dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
+ ret);
+ return ret;
+ }
+
+ dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
+
+ attrs = DMA_ATTR_NO_KERNEL_MAPPING;
+
+ cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
+ if (!cpu_addr) {
+ dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
+ psize);
+ return -ENOMEM;
+ }
+
+ ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
+ if (ret) {
+ dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
+ goto free_mem;
+ }
+
+ allocated = true;
+ return 0;
+
+free_mem:
+ dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
+ return ret;
+}
+
static int qcom_iommu_ctx_probe(struct platform_device *pdev)
{
struct qcom_iommu_ctx *ctx;
@@ -688,6 +733,17 @@ static struct platform_driver qcom_iommu_ctx_driver = {
};
module_platform_driver(qcom_iommu_ctx_driver);
+static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
+{
+ struct device_node *child;
+
+ for_each_child_of_node(qcom_iommu->dev->of_node, child)
+ if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec"))
+ return true;
+
+ return false;
+}
+
static int qcom_iommu_device_probe(struct platform_device *pdev)
{
struct qcom_iommu_dev *qcom_iommu;
@@ -724,6 +780,14 @@ static int qcom_iommu_device_probe(struct platform_device *pdev)
return -ENODEV;
}
+ if (qcom_iommu_has_secure_context(qcom_iommu)) {
+ ret = qcom_iommu_sec_ptbl_init(dev);
+ if (ret) {
+ dev_err(dev, "cannot init secure pg table(%d)\n", ret);
+ return ret;
+ }
+ }
+
platform_set_drvdata(pdev, qcom_iommu);
/* register context bank devices, which are child nodes: */
--
2.9.3
next prev parent reply other threads:[~2017-03-14 15:18 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-14 15:18 [PATCH 0/9] iommu: add qcom_iommu for early "B" family devices (v2) Rob Clark
[not found] ` <20170314151811.17234-1-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-14 15:18 ` [PATCH 1/9] firmware/qcom: add qcom_scm_restore_sec_cfg() Rob Clark
2017-03-14 15:18 ` [PATCH 2/9] firmware: qcom_scm: add two scm calls for iommu secure page table Rob Clark
2017-03-14 15:18 ` [PATCH 3/9] Docs: dt: document qcom iommu bindings Rob Clark
[not found] ` <20170314151811.17234-4-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-23 22:21 ` Rob Herring
2017-03-24 2:45 ` Rob Clark
2017-03-27 19:10 ` Rob Herring
2017-03-14 15:18 ` [PATCH 4/9] iommu: arm-smmu: split out register defines Rob Clark
2017-03-14 15:18 ` [PATCH 5/9] iommu: add qcom_iommu Rob Clark
[not found] ` <20170314151811.17234-6-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-30 6:19 ` Archit Taneja
2017-03-30 13:46 ` Rob Clark
2017-03-31 4:19 ` Archit Taneja
2017-03-14 15:18 ` Rob Clark [this message]
2017-03-14 15:18 ` [PATCH 7/9] ARM64: DT: add gpu for msm8916 Rob Clark
2017-03-14 15:18 ` [PATCH 8/9] ARM64: DT: add video codec devicetree node Rob Clark
2017-03-14 15:18 ` [PATCH 9/9] ARM64: DT: add iommu for msm8916 Rob Clark
-- strict thread matches above, loose matches on Subject: below --
2017-03-01 17:42 [PATCH 0/9] iommu: add qcom_iommu for early "B" family devices Rob Clark
2017-03-01 17:42 ` [PATCH 6/9] iommu: qcom: initialize secure page table Rob Clark
[not found] ` <20170301174258.14618-7-robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-01 22:14 ` Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170314151811.17234-7-robdclark@gmail.com \
--to=robdclark@gmail.com \
--cc=iommu@lists.linux-foundation.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=robin.murphy@arm.com \
--cc=sricharan@codeaurora.org \
--cc=stanimir.varbanov@linaro.org \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).