From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: [PATCH 09/24] drm/msm/mdp5: Prepare for dynamic assignment of mixers
Date: Thu, 23 Mar 2017 15:58:02 +0530 [thread overview]
Message-ID: <20170323102817.15017-10-architt@codeaurora.org> (raw)
In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org>
Add the stuff needed to allow dynamically assigning a mixer to a CRTC.
Since mixers are a resource that can be shared across multiple CRTCs, we
need to maintain a 'hwmixer_to_crtc' map in the global atomic state,
acquire the mdp5_kms.state_lock modeset lock and so on.
The mixer is assigned in the CRTC's atomic_check() func, a failure will
result in the new state being cleanly rolled back.
The mixer assignment itself is straightforward, and almost identical to
what we do for hwpipes. We don't need to grab the old hwmixer_to_crtc
state like we do in hwpipes since we don't need to compare anything
with the old state at the moment.
The only LM capability we care about at the moment is whether the mixer
instance can be used to display stuff (i.e, connect to an INTF
downstream).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 31 +++++++++++++++++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.c | 55 +++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.h | 9 +++++
5 files changed, 97 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 09ea7c3d8951..0f6e545d74ba 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -373,6 +373,30 @@ static void mdp5_crtc_enable(struct drm_crtc *crtc)
mdp5_crtc->enabled = true;
}
+int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
+ struct drm_crtc_state *new_crtc_state)
+{
+ struct mdp5_crtc_state *mdp5_cstate =
+ to_mdp5_crtc_state(new_crtc_state);
+ struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
+ bool new_mixer = false;
+
+ new_mixer = !pipeline->mixer;
+
+ if (new_mixer) {
+ struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
+
+ pipeline->mixer = mdp5_mixer_assign(new_crtc_state->state, crtc,
+ MDP_LM_CAP_DISPLAY);
+ if (IS_ERR(pipeline->mixer))
+ return PTR_ERR(pipeline->mixer);
+
+ mdp5_mixer_release(new_crtc_state->state, old_mixer);
+ }
+
+ return 0;
+}
+
struct plane_state {
struct drm_plane *plane;
struct mdp5_plane_state *state;
@@ -405,6 +429,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
const struct drm_plane_state *pstate;
bool cursor_plane = false;
int cnt = 0, base = 0, i;
+ int ret;
DBG("%s: check", crtc->name);
@@ -418,6 +443,12 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
cursor_plane = true;
}
+ ret = mdp5_crtc_setup_pipeline(crtc, state);
+ if (ret) {
+ dev_err(dev->dev, "couldn't assign mixers %d\n", ret);
+ return ret;
+ }
+
/* assign a stage based on sorted zpos property */
sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 9dcd893a5c06..9525c990f2dc 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -90,6 +90,7 @@ struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s)
/* Copy state: */
new_state->hwpipe = mdp5_kms->state->hwpipe;
+ new_state->hwmixer = mdp5_kms->state->hwmixer;
if (mdp5_kms->smp)
new_state->smp = mdp5_kms->state->smp;
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index b875f453b930..535848e93f55 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -96,6 +96,7 @@ struct mdp5_kms {
*/
struct mdp5_state {
struct mdp5_hw_pipe_state hwpipe;
+ struct mdp5_hw_mixer_state hwmixer;
struct mdp5_smp_state smp;
};
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.c
index 032dc0a9638f..6f353c4886e4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.c
@@ -16,6 +16,61 @@
#include "mdp5_kms.h"
+struct mdp5_hw_mixer *mdp5_mixer_assign(struct drm_atomic_state *s,
+ struct drm_crtc *crtc, uint32_t caps)
+{
+ struct msm_drm_private *priv = s->dev->dev_private;
+ struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
+ struct mdp5_state *state = mdp5_get_state(s);
+ struct mdp5_hw_mixer_state *new_state;
+ struct mdp5_hw_mixer *mixer = NULL;
+ int i;
+
+ if (IS_ERR(state))
+ return ERR_CAST(state);
+
+ new_state = &state->hwmixer;
+
+ for (i = 0; i < mdp5_kms->num_hwmixers; i++) {
+ struct mdp5_hw_mixer *cur = mdp5_kms->hwmixers[i];
+
+ /* skip if already in-use */
+ if (new_state->hwmixer_to_crtc[cur->idx])
+ continue;
+
+ /* skip if doesn't support some required caps: */
+ if (caps & ~cur->caps)
+ continue;
+
+ if (!mixer)
+ mixer = cur;
+ }
+
+ if (!mixer)
+ return ERR_PTR(-ENOMEM);
+
+ new_state->hwmixer_to_crtc[mixer->idx] = crtc;
+
+ return mixer;
+}
+
+void mdp5_mixer_release(struct drm_atomic_state *s, struct mdp5_hw_mixer *mixer)
+{
+ struct mdp5_state *state = mdp5_get_state(s);
+ struct mdp5_hw_mixer_state *new_state = &state->hwmixer;
+
+ if (!mixer)
+ return;
+
+ if (WARN_ON(!new_state->hwmixer_to_crtc[mixer->idx]))
+ return;
+
+ DBG("%s: release from crtc %s", mixer->name,
+ new_state->hwmixer_to_crtc[mixer->idx]->name);
+
+ new_state->hwmixer_to_crtc[mixer->idx] = NULL;
+}
+
void mdp5_mixer_destroy(struct mdp5_hw_mixer *mixer)
{
kfree(mixer);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.h
index 08d2173703bf..18ed933ae574 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mixer.h
@@ -31,7 +31,16 @@ struct mdp5_hw_mixer {
uint32_t flush_mask; /* used to commit LM registers */
};
+/* global atomic state of assignment between CRTCs and Layer Mixers: */
+struct mdp5_hw_mixer_state {
+ struct drm_crtc *hwmixer_to_crtc[8];
+};
+
struct mdp5_hw_mixer *mdp5_mixer_init(const struct mdp5_lm_instance *lm);
void mdp5_mixer_destroy(struct mdp5_hw_mixer *lm);
+struct mdp5_hw_mixer *mdp5_mixer_assign(struct drm_atomic_state *s,
+ struct drm_crtc *crtc, uint32_t caps);
+void mdp5_mixer_release(struct drm_atomic_state *s,
+ struct mdp5_hw_mixer *mixer);
#endif /* __MDP5_LM_H__ */
--
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next prev parent reply other threads:[~2017-03-23 10:28 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-23 10:27 [PATCH 00/24] drm/msm/mdp5: Mixer virtualization and 4K plane support Archit Taneja
2017-03-23 10:27 ` [PATCH 01/24] drm/msm/mdp5: Bring back pipe_lock to mdp5_plane struct Archit Taneja
2017-03-23 10:27 ` [PATCH 02/24] drm/msm/mdp5: describe LM instances in mdp5_cfg Archit Taneja
2017-03-23 10:27 ` [PATCH 03/24] drm/msm/mdp5: Add structs for hw Layer Mixers Archit Taneja
2017-03-23 10:27 ` [PATCH 04/24] drm/msm/mdp5: Start using mdp5_hw_mixer Archit Taneja
2017-03-23 10:27 ` [PATCH 05/24] drm/msm/mdp5: Simplify LM <-> PP mapping Archit Taneja
2017-03-23 10:27 ` [PATCH 06/24] drm/msm/mdp5: Clean up interface assignment Archit Taneja
2017-03-23 10:28 ` [PATCH 07/24] drm/msm/mdp5: Remove the pipeline stuff in mdp5_ctl Archit Taneja
2017-03-23 10:28 ` [PATCH 08/24] drm/msm/mdp5: subclass CRTC state Archit Taneja
2017-03-23 10:28 ` Archit Taneja [this message]
2017-03-23 10:28 ` [PATCH 10/24] drm/msm/mdp5: Assign INTF and CTL in encoder's atomic_check() Archit Taneja
2017-03-23 10:28 ` [PATCH 11/24] drm/msm/mdp5: Add more stuff to CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 12/24] drm/msm/mdp5: Start using parameters from " Archit Taneja
2017-03-23 10:28 ` [PATCH 13/24] drm/msm/mdp5: Remove mixer/intf pointers from mdp5_ctl Archit Taneja
2017-03-23 10:28 ` [PATCH 14/24] drm/msm/mdp5: Add a CAP for Source Split Archit Taneja
2017-03-23 10:28 ` [PATCH 15/24] drm/msm/mdp5: Add optional 'right' Layer Mixer in CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 16/24] drm/msm/mdp5: Create mdp5_hwpipe_mode_set Archit Taneja
2017-03-23 10:28 ` [PATCH 17/24] drm/msm/mdp5: Assign a 'right hwpipe' to plane state Archit Taneja
2017-03-23 10:28 ` [PATCH 18/24] drm/msm/mdp5: Configure 'right' hwpipe Archit Taneja
2017-03-23 10:28 ` [PATCH 19/24] drm/msm/mdp5: Prepare Layer Mixers for source split Archit Taneja
2017-03-23 10:28 ` [PATCH 20/24] drm/msm/mdp5: Stage right side hwpipes on Right-side Layer Mixer Archit Taneja
2017-03-23 10:28 ` [PATCH 21/24] drm/msm/mdp5: Stage border out on base stage if CRTC has 2 LMs Archit Taneja
2017-03-23 10:28 ` [PATCH 22/24] drm/msm/mdp5: Assign 'right' mixer to CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 23/24] drm/msm/mdp5: Reset CTL blend registers before configuring them Archit Taneja
2017-03-23 10:28 ` [PATCH 24/24] drm/msm/mdp5: Enable 3D mux in mdp5_ctl Archit Taneja
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