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From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	Archit Taneja <architt@codeaurora.org>
Subject: [PATCH 10/24] drm/msm/mdp5: Assign INTF and CTL in encoder's atomic_check()
Date: Thu, 23 Mar 2017 15:58:03 +0530	[thread overview]
Message-ID: <20170323102817.15017-11-architt@codeaurora.org> (raw)
In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org>

The INTF and CTL used in a display pipeline are going to be maintained as
a part of the CRTC state (i.e, in mdp5_crtc_state).

These entities, however, are currently statically assigned to drm_encoders
(i.e. mdp5_encoder). Since these aren't directly visible to the CRTC, we
assign them to the CRTC state in the encoder's atomic_check() op.

With this approach, we assign portions of CRTC state in two different
places: the layer mixer in CRTC's atomic_check(), and the INTF and CTL
pieces in the encoder's atomic_check() op.

We'd have more options here if the drm core maintained encoder state too,
but the current approach of clubbing everything in CRTC's state works just
fine.

Unlike hwpipes and mixers, we don't need to keep a track of INTF/CTL
assignments in the global atomic state. This is because they're currently
not sharable resources. For example, INTF0 and CTL0 will always be assigned
to one drm_encoder. This can change later when we implement writeback and
want a CRTC to use a CTL for a while, and then release it for others to use
it. Or, when a drm_encoder can switch between using a single INTF vs
2 INTFs.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
index 2994841eb00c..6d535140ef21 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -303,10 +303,26 @@ static void mdp5_encoder_enable(struct drm_encoder *encoder)
 		mdp5_vid_encoder_enable(encoder);
 }
 
+static int mdp5_encoder_atomic_check(struct drm_encoder *encoder,
+				     struct drm_crtc_state *crtc_state,
+				     struct drm_connector_state *conn_state)
+{
+	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
+	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
+	struct mdp5_interface *intf = mdp5_encoder->intf;
+	struct mdp5_ctl *ctl = mdp5_encoder->ctl;
+
+	mdp5_cstate->ctl = ctl;
+	mdp5_cstate->pipeline.intf = intf;
+
+	return 0;
+}
+
 static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
 	.mode_set = mdp5_encoder_mode_set,
 	.disable = mdp5_encoder_disable,
 	.enable = mdp5_encoder_enable,
+	.atomic_check = mdp5_encoder_atomic_check,
 };
 
 int mdp5_encoder_get_linecount(struct drm_encoder *encoder)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

  parent reply	other threads:[~2017-03-23 10:29 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-23 10:27 [PATCH 00/24] drm/msm/mdp5: Mixer virtualization and 4K plane support Archit Taneja
2017-03-23 10:27 ` [PATCH 01/24] drm/msm/mdp5: Bring back pipe_lock to mdp5_plane struct Archit Taneja
2017-03-23 10:27 ` [PATCH 02/24] drm/msm/mdp5: describe LM instances in mdp5_cfg Archit Taneja
2017-03-23 10:27 ` [PATCH 03/24] drm/msm/mdp5: Add structs for hw Layer Mixers Archit Taneja
2017-03-23 10:27 ` [PATCH 04/24] drm/msm/mdp5: Start using mdp5_hw_mixer Archit Taneja
2017-03-23 10:27 ` [PATCH 05/24] drm/msm/mdp5: Simplify LM <-> PP mapping Archit Taneja
2017-03-23 10:27 ` [PATCH 06/24] drm/msm/mdp5: Clean up interface assignment Archit Taneja
2017-03-23 10:28 ` [PATCH 07/24] drm/msm/mdp5: Remove the pipeline stuff in mdp5_ctl Archit Taneja
2017-03-23 10:28 ` [PATCH 08/24] drm/msm/mdp5: subclass CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 09/24] drm/msm/mdp5: Prepare for dynamic assignment of mixers Archit Taneja
2017-03-23 10:28 ` Archit Taneja [this message]
2017-03-23 10:28 ` [PATCH 11/24] drm/msm/mdp5: Add more stuff to CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 12/24] drm/msm/mdp5: Start using parameters from " Archit Taneja
2017-03-23 10:28 ` [PATCH 13/24] drm/msm/mdp5: Remove mixer/intf pointers from mdp5_ctl Archit Taneja
2017-03-23 10:28 ` [PATCH 14/24] drm/msm/mdp5: Add a CAP for Source Split Archit Taneja
2017-03-23 10:28 ` [PATCH 15/24] drm/msm/mdp5: Add optional 'right' Layer Mixer in CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 16/24] drm/msm/mdp5: Create mdp5_hwpipe_mode_set Archit Taneja
2017-03-23 10:28 ` [PATCH 17/24] drm/msm/mdp5: Assign a 'right hwpipe' to plane state Archit Taneja
2017-03-23 10:28 ` [PATCH 18/24] drm/msm/mdp5: Configure 'right' hwpipe Archit Taneja
2017-03-23 10:28 ` [PATCH 19/24] drm/msm/mdp5: Prepare Layer Mixers for source split Archit Taneja
2017-03-23 10:28 ` [PATCH 20/24] drm/msm/mdp5: Stage right side hwpipes on Right-side Layer Mixer Archit Taneja
2017-03-23 10:28 ` [PATCH 21/24] drm/msm/mdp5: Stage border out on base stage if CRTC has 2 LMs Archit Taneja
2017-03-23 10:28 ` [PATCH 22/24] drm/msm/mdp5: Assign 'right' mixer to CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 23/24] drm/msm/mdp5: Reset CTL blend registers before configuring them Archit Taneja
2017-03-23 10:28 ` [PATCH 24/24] drm/msm/mdp5: Enable 3D mux in mdp5_ctl Archit Taneja

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