From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>
Subject: [PATCH 20/24] drm/msm/mdp5: Stage right side hwpipes on Right-side Layer Mixer
Date: Thu, 23 Mar 2017 15:58:13 +0530 [thread overview]
Message-ID: <20170323102817.15017-21-architt@codeaurora.org> (raw)
In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org>
Now that our mdp5_planes can consist of 2 hwpipes, update the
blend_setup() code to stage the right hwpipe to the left and
right LMs
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 12 ++++++++++++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 12 ++++++++----
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 4b3bc5fc1006..cf6d41c9edc7 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -245,6 +245,8 @@ static void blend_setup(struct drm_crtc *crtc)
/* Collect all plane information */
drm_atomic_crtc_for_each_plane(plane, crtc) {
+ enum mdp5_pipe right_pipe;
+
pstate = to_mdp5_plane_state(plane->state);
pstates[pstate->stage] = pstate;
stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
@@ -255,6 +257,16 @@ static void blend_setup(struct drm_crtc *crtc)
if (r_mixer)
r_stage[pstate->stage][PIPE_LEFT] =
mdp5_plane_pipe(plane);
+ /*
+ * if we have a right pipe (i.e, the plane comprises of 2
+ * hwpipes, then stage the right pipe on the right side of both
+ * the layer mixers
+ */
+ right_pipe = mdp5_plane_right_pipe(plane);
+ if (right_pipe) {
+ stage[pstate->stage][PIPE_RIGHT] = right_pipe;
+ r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
+ }
plane_cnt++;
}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 1fdbb936877f..15d78b218935 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -380,14 +380,18 @@ int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
for (i = start_stage; stage_cnt && i <= STAGE_MAX; i++) {
blend_cfg |=
- mdp_ctl_blend_mask(stage[i][PIPE_LEFT], i);
+ mdp_ctl_blend_mask(stage[i][PIPE_LEFT], i) |
+ mdp_ctl_blend_mask(stage[i][PIPE_RIGHT], i);
blend_ext_cfg |=
- mdp_ctl_blend_ext_mask(stage[i][PIPE_LEFT], i);
+ mdp_ctl_blend_ext_mask(stage[i][PIPE_LEFT], i) |
+ mdp_ctl_blend_ext_mask(stage[i][PIPE_RIGHT], i);
if (r_mixer) {
r_blend_cfg |=
- mdp_ctl_blend_mask(r_stage[i][PIPE_LEFT], i);
+ mdp_ctl_blend_mask(r_stage[i][PIPE_LEFT], i) |
+ mdp_ctl_blend_mask(r_stage[i][PIPE_RIGHT], i);
r_blend_ext_cfg |=
- mdp_ctl_blend_ext_mask(r_stage[i][PIPE_LEFT], i);
+ mdp_ctl_blend_ext_mask(r_stage[i][PIPE_LEFT], i) |
+ mdp_ctl_blend_ext_mask(r_stage[i][PIPE_RIGHT], i);
}
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
next prev parent reply other threads:[~2017-03-23 10:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-23 10:27 [PATCH 00/24] drm/msm/mdp5: Mixer virtualization and 4K plane support Archit Taneja
2017-03-23 10:27 ` [PATCH 01/24] drm/msm/mdp5: Bring back pipe_lock to mdp5_plane struct Archit Taneja
2017-03-23 10:27 ` [PATCH 02/24] drm/msm/mdp5: describe LM instances in mdp5_cfg Archit Taneja
2017-03-23 10:27 ` [PATCH 03/24] drm/msm/mdp5: Add structs for hw Layer Mixers Archit Taneja
2017-03-23 10:27 ` [PATCH 04/24] drm/msm/mdp5: Start using mdp5_hw_mixer Archit Taneja
2017-03-23 10:27 ` [PATCH 05/24] drm/msm/mdp5: Simplify LM <-> PP mapping Archit Taneja
2017-03-23 10:27 ` [PATCH 06/24] drm/msm/mdp5: Clean up interface assignment Archit Taneja
2017-03-23 10:28 ` [PATCH 07/24] drm/msm/mdp5: Remove the pipeline stuff in mdp5_ctl Archit Taneja
2017-03-23 10:28 ` [PATCH 08/24] drm/msm/mdp5: subclass CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 09/24] drm/msm/mdp5: Prepare for dynamic assignment of mixers Archit Taneja
2017-03-23 10:28 ` [PATCH 10/24] drm/msm/mdp5: Assign INTF and CTL in encoder's atomic_check() Archit Taneja
2017-03-23 10:28 ` [PATCH 11/24] drm/msm/mdp5: Add more stuff to CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 12/24] drm/msm/mdp5: Start using parameters from " Archit Taneja
2017-03-23 10:28 ` [PATCH 13/24] drm/msm/mdp5: Remove mixer/intf pointers from mdp5_ctl Archit Taneja
2017-03-23 10:28 ` [PATCH 14/24] drm/msm/mdp5: Add a CAP for Source Split Archit Taneja
2017-03-23 10:28 ` [PATCH 15/24] drm/msm/mdp5: Add optional 'right' Layer Mixer in CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 16/24] drm/msm/mdp5: Create mdp5_hwpipe_mode_set Archit Taneja
2017-03-23 10:28 ` [PATCH 17/24] drm/msm/mdp5: Assign a 'right hwpipe' to plane state Archit Taneja
2017-03-23 10:28 ` [PATCH 18/24] drm/msm/mdp5: Configure 'right' hwpipe Archit Taneja
2017-03-23 10:28 ` [PATCH 19/24] drm/msm/mdp5: Prepare Layer Mixers for source split Archit Taneja
2017-03-23 10:28 ` Archit Taneja [this message]
2017-03-23 10:28 ` [PATCH 21/24] drm/msm/mdp5: Stage border out on base stage if CRTC has 2 LMs Archit Taneja
2017-03-23 10:28 ` [PATCH 22/24] drm/msm/mdp5: Assign 'right' mixer to CRTC state Archit Taneja
2017-03-23 10:28 ` [PATCH 23/24] drm/msm/mdp5: Reset CTL blend registers before configuring them Archit Taneja
2017-03-23 10:28 ` [PATCH 24/24] drm/msm/mdp5: Enable 3D mux in mdp5_ctl Archit Taneja
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