From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: Re: [PATCH v5] drm/msm: gpu: Enable zap shader for A5XX Date: Wed, 17 May 2017 13:37:01 -0700 Message-ID: <20170517203701.GJ12920@tuxbook> References: <1495032329-27652-1-git-send-email-jcrouse@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from mail-qt0-f177.google.com ([209.85.216.177]:35597 "EHLO mail-qt0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752277AbdEQUhB (ORCPT ); Wed, 17 May 2017 16:37:01 -0400 Received: by mail-qt0-f177.google.com with SMTP id v27so19541134qtg.2 for ; Wed, 17 May 2017 13:37:01 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1495032329-27652-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Jordan Crouse Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org On Wed 17 May 07:45 PDT 2017, Jordan Crouse wrote: > The A5XX GPU powers on in "secure" mode. In secure mode the GPU can > only render to buffers that are marked as secure and inaccessible > to the kernel and user through a series of hardware protections. In > practice secure mode is used to draw things like a UI on a secure > video frame. > > In order to switch out of secure mode the GPU executes a special > shader that clears out the GMEM and other sensitve registers and > then writes a register. Because the kernel can't be trusted the > shader binary is signed and verified and programmed by the > secure world. To do this we need to read the MDT header and the > segments from the firmware location and put them in memory and > present them for approval. > > For targets without secure support there is an out: if the > secure world doesn't support secure then there are no hardware > protections and we can freely write the SECVID_TRUST register from > the CPU. We don't have 100% confidence that we can query the > secure capabilities at run time but we have enough calls that > need to go right to give us some confidence that we're at least doing > something useful. > > Of course if we guess wrong you trigger a permissions violation > which usually ends up in a system crash but thats a problem > that shows up immediately. > > [v2: use child device per Bjorn] > [v3: use generic MDT loader per Bjorn] > [v4: use managed dma functions and ifdefs for the MDT loader] > [v5: Add depends for QCOM_MDT_LOADER] > > Signed-off-by: Jordan Crouse > --- > drivers/gpu/drm/msm/Kconfig | 1 + > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 180 ++++++++++++++++++++++++++++- > drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 2 + > drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > 5 files changed, 183 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > index 5b8e23d..b29bd30 100644 > --- a/drivers/gpu/drm/msm/Kconfig > +++ b/drivers/gpu/drm/msm/Kconfig > @@ -5,6 +5,7 @@ config DRM_MSM > depends on ARCH_QCOM || (ARM && COMPILE_TEST) > depends on OF && COMMON_CLK > depends on MMU > + depends on QCOM_MDT_LOADER || QCOM_MDT_LOADER=n > select REGULATOR > select DRM_KMS_HELPER > select DRM_PANEL > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 31a9bce..058cb80 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -11,6 +11,12 @@ > * > */ > > +#include > +#include > +#include > +#include > +#include > +#include > #include "msm_gem.h" > #include "msm_mmu.h" > #include "a5xx_gpu.h" > @@ -18,6 +24,62 @@ > extern bool hang_debug; > static void a5xx_dump(struct msm_gpu *gpu); > > +#define GPU_PAS_ID 13 > + > +#ifdef CONFIG_QCOM_MDT_LOADER #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) Apart from that Acked-by: Bjorn Andersson Regards, Bjorn