From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH 5/5 v2] clk: qcom: Add support for MSM8660 LCC
Date: Sat, 27 May 2017 13:19:13 -0700 [thread overview]
Message-ID: <20170527201913.GN12920@tuxbook> (raw)
In-Reply-To: <20170419091326.11226-5-linus.walleij@linaro.org>
On Wed 19 Apr 02:13 PDT 2017, Linus Walleij wrote:
> diff --git a/drivers/clk/qcom/lcc-msm8660.c b/drivers/clk/qcom/lcc-msm8660.c
[..]
> +/* The vendor code uses PLL4 as parent everywhere */
> +static const struct parent_map lcc_parent_map[] = {
> + { P_PXO, 0 },
> + { P_CXO, 1 },
> + /* Select RPM PLL4, but also used for selecting LPA PLL0 */
> + { P_PLL4_LPA_PLL0, 2 },
> + /* Will just ground the line */
> + { P_GND, 6 },
> +};
> +
> +static const char * const lcc_parent_tbl[] = {
> + "pxo",
> + "cxo",
> + /*
> + * PLL4 is an RPM clock on MSM8660/APQ8060, set to "pll4" for this
> + * If we enable and mux in the LPA_PLL0 on this platform, we can
> + * set this to "lpa_pll0" instead
> + */
> + "pll4_clk",
> + "gnd", /* This is a very inactive parent */
> +};
> +
> +/*
> + * This table is evidently for using PLL4 as parent, if we start using
> + * LPA_PLL0 we need to provide a second table.
> + */
Aren't you muxing in LPA_PLL0 as source instead of PLL4 at the bottom of
probe()? And as you hard code that selector, shouldn't the parent table
reference lpa_pll0?
> +static struct freq_tbl clk_tbl_aif_osr_pll4[] = {
> + { 768000, P_PLL4_LPA_PLL0, 4, 1, 176 },
> + { 1024000, P_PLL4_LPA_PLL0, 4, 1, 132 },
> + { 1536000, P_PLL4_LPA_PLL0, 4, 1, 88 },
> + { 2048000, P_PLL4_LPA_PLL0, 4, 1, 66 },
> + { 3072000, P_PLL4_LPA_PLL0, 4, 1, 44 },
> + { 4096000, P_PLL4_LPA_PLL0, 4, 1, 33 },
> + { 6144000, P_PLL4_LPA_PLL0, 4, 1, 22 },
> + { 8192000, P_PLL4_LPA_PLL0, 2, 1, 33 },
> + { 12288000, P_PLL4_LPA_PLL0, 4, 1, 11 },
> + { 24576000, P_PLL4_LPA_PLL0, 2, 1, 11 },
> + { 27000000, P_PXO, 1, 0, 0 },
> + { }
> +};
> +
[..]
> +static int lcc_msm8660_probe(struct platform_device *pdev)
> +{
[..]
> + /*
> + * Enable LPA_PLL0 source on the LPASS Primary PLL Mux. Incidentally
> + * this is set to 0x00000001 at boot.
> + * 0x01 = LPA_PLL0
> + */
> + regmap_write(regmap, 0xc4, 0x1);
Regards,
Bjorn
next prev parent reply other threads:[~2017-05-27 20:19 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-19 9:13 [PATCH 1/5 v2] clk: qcom: Update DT bindings for the MSM8660/APQ8060 RPMCC Linus Walleij
2017-04-19 9:13 ` [PATCH 2/5 v2] clk: qcom: Elaborate on "active" clocks in the RPM clock bindings Linus Walleij
[not found] ` <20170419091326.11226-2-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2017-04-28 13:35 ` Rob Herring
2017-06-01 7:39 ` Stephen Boyd
2017-04-19 9:13 ` [PATCH 3/5 v2] clk: qcom: Implement RPM clocks for MSM8660/APQ8060 Linus Walleij
2017-05-27 20:00 ` Bjorn Andersson
2017-06-01 8:05 ` Stephen Boyd
2017-10-13 11:50 ` Linus Walleij
2017-06-01 7:58 ` Stephen Boyd
2017-04-19 9:13 ` [PATCH 4/5 v2] clk: qcom: Update DT bindings for MSM8660 LCC Linus Walleij
2017-04-19 9:13 ` [PATCH 5/5 v2] clk: qcom: Add support " Linus Walleij
2017-05-27 20:19 ` Bjorn Andersson [this message]
2017-05-29 12:23 ` Linus Walleij
2017-05-30 19:24 ` Bjorn Andersson
2017-06-01 7:33 ` Stephen Boyd
2017-06-01 8:20 ` Stephen Boyd
2017-05-17 7:23 ` [PATCH 1/5 v2] clk: qcom: Update DT bindings for the MSM8660/APQ8060 RPMCC Linus Walleij
[not found] ` <CACRpkdbXEFeVkD8rETyrnuoAxUvnFt2BL07UsXuXfSnq3Qdyfw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-05-24 9:16 ` Linus Walleij
[not found] ` <CACRpkdYvwwJcxKPtKUyZBLWsmjXji7pHDKNz9NRTETqj2P3drQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-05-26 11:57 ` Peter De Schrijver
2017-06-01 7:38 ` Stephen Boyd
2017-06-09 8:48 ` Linus Walleij
[not found] ` <20170419091326.11226-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2017-06-01 7:48 ` Stephen Boyd
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