From: Archit Taneja <architt@codeaurora.org>
To: robdclark@gmail.com
Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
Archit Taneja <architt@codeaurora.org>
Subject: [PATCH 1/2] rnndb: hdmi: Fix HDMI timing bitfields for 8x96
Date: Fri, 16 Jun 2017 10:41:08 +0530 [thread overview]
Message-ID: <20170616051109.1886-1-architt@codeaurora.org> (raw)
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
rnndb/hdmi/hdmi.xml | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/rnndb/hdmi/hdmi.xml b/rnndb/hdmi/hdmi.xml
index 69b4828..2bbae43 100644
--- a/rnndb/hdmi/hdmi.xml
+++ b/rnndb/hdmi/hdmi.xml
@@ -457,25 +457,25 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
<reg32 offset="0x002b4" name="ACTIVE_HSYNC">
- <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="START" low="0" high="12" type="uint"/>
<bitfield name="END" low="16" high="27" type="uint"/>
</reg32>
<reg32 offset="0x002b8" name="ACTIVE_VSYNC">
- <bitfield name="START" low="0" high="11" type="uint"/>
- <bitfield name="END" low="16" high="27" type="uint"/>
+ <bitfield name="START" low="0" high="12" type="uint"/>
+ <bitfield name="END" low="16" high="28" type="uint"/>
</reg32>
<reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
<!-- interlaced, frame 2 -->
- <bitfield name="START" low="0" high="11" type="uint"/>
- <bitfield name="END" low="16" high="27" type="uint"/>
+ <bitfield name="START" low="0" high="12" type="uint"/>
+ <bitfield name="END" low="16" high="28" type="uint"/>
</reg32>
<reg32 offset="0x002c0" name="TOTAL">
- <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
- <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
+ <bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
+ <bitfield name="V_TOTAL" low="16" high="28" type="uint"/>
</reg32>
<reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
<!-- interlaced, frame 2 -->
- <bitfield name="V_TOTAL" low="0" high="11" type="uint"/>
+ <bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
</reg32>
<reg32 offset="0x002c8" name="FRAME_CTRL">
<bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
--
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next reply other threads:[~2017-06-16 5:11 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-16 5:11 Archit Taneja [this message]
2017-06-16 5:11 ` [PATCH 2/2] rnndb: hdmi: Add register HDMI_INFOFRAME_CTRL1 Archit Taneja
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