From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: Re: [PATCH] ARM: dts: qcom: add MSM8660 GSBI6 and GSBI7 Date: Tue, 10 Oct 2017 11:07:48 -0700 Message-ID: <20171010180748.GC1165@minitux> References: <20171010083924.19244-1-linus.walleij@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from mail-pf0-f172.google.com ([209.85.192.172]:46509 "EHLO mail-pf0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932597AbdJJSHw (ORCPT ); Tue, 10 Oct 2017 14:07:52 -0400 Received: by mail-pf0-f172.google.com with SMTP id p87so8997801pfj.3 for ; Tue, 10 Oct 2017 11:07:52 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20171010083924.19244-1-linus.walleij@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Andy Gross , David Brown , Stephen Boyd , linux-soc@vger.kernel.org On Tue 10 Oct 01:39 PDT 2017, Linus Walleij wrote: > This adds the GSBI6 and GSBI7 IO blocks to the MSM8660 DTSI file. > On the APQ8060 DragonBoard, GSBI6 DM is used for Bluetooth UART, > and GSBI7 I2C is used for FM radio I2C. > > Signed-off-by: Linus Walleij Acked-by: Bjorn Andersson Regards, Bjorn > --- > arch/arm/boot/dts/qcom-msm8660.dtsi | 67 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi > index 1b5d31b33b5e..4f02489bcb2e 100644 > --- a/arch/arm/boot/dts/qcom-msm8660.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi > @@ -123,6 +123,73 @@ > reg = <0x900000 0x4000>; > }; > > + gsbi6: gsbi@16500000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <12>; > + reg = <0x16500000 0x100>; > + clocks = <&gcc GSBI6_H_CLK>; > + clock-names = "iface"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + syscon-tcsr = <&tcsr>; > + > + gsbi6_serial: serial@16540000 { > + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; > + reg = <0x16540000 0x1000>, > + <0x16500000 0x1000>; > + interrupts = ; > + clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > + gsbi6_i2c: i2c@16580000 { > + compatible = "qcom,i2c-qup-v1.1.1"; > + reg = <0x16580000 0x1000>; > + interrupts = ; > + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; > + clock-names = "core", "iface"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + > + gsbi7: gsbi@16600000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <12>; > + reg = <0x16600000 0x100>; > + clocks = <&gcc GSBI7_H_CLK>; > + clock-names = "iface"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + syscon-tcsr = <&tcsr>; > + > + gsbi7_serial: serial@16640000 { > + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; > + reg = <0x16640000 0x1000>, > + <0x16600000 0x1000>; > + interrupts = ; > + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > + gsbi7_i2c: i2c@16680000 { > + compatible = "qcom,i2c-qup-v1.1.1"; > + reg = <0x16680000 0x1000>; > + interrupts = ; > + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; > + clock-names = "core", "iface"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > > gsbi8: gsbi@19800000 { > compatible = "qcom,gsbi-v1.0.0"; > -- > 2.13.5 >