From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 05/13] clk: qcom: add and use alpha register width from PLL properties Date: Fri, 8 Dec 2017 16:18:51 -0800 Message-ID: <20171209001851.GJ7997@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> <1506621050-10129-6-git-send-email-absahu@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <1506621050-10129-6-git-send-email-absahu@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Abhishek Sahu Cc: Michael Turquette , Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org On 09/28, Abhishek Sahu wrote: > Currently SUPPORTS_16BIT_ALPHA flag determines the PLL alpha > register width. If this flag is set then the alpha register width > is 16 bits otherwise it is 40 bits. The alpha width is always > fixed for PLL type so it can be added in PLL properties and clock > driver don’t have to specify explicitly. > > The SUPPORTS_16BIT_ALPHA flag is unused in the current code so > it’s safe to remove this flags. > > Signed-off-by: Abhishek Sahu > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project