From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation Date: Fri, 8 Dec 2017 16:18:53 -0800 Message-ID: <20171209001853.GK7997@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> <1506621050-10129-5-git-send-email-absahu@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1506621050-10129-5-git-send-email-absahu@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org To: Abhishek Sahu Cc: Michael Turquette , Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org On 09/28, Abhishek Sahu wrote: > The alpha value calculation function has been written for 40 bit > alpha which is not coming properly for 16 bit > > 1. Alpha value is being calculated on the basis of > ALPHA_BITWIDTH to make the computation easy for 40 bit alpha. > After calculating the 32 bit alpha, It is being converted to 40 > bit alpha by making making lower bits zero. But if actual alpha > register width is less than ALPHA_BITWIDTH, then the actual width > can be used for calculation > > 2. During 40 bit alpha pll set rate, the lower alpha register is > not being configured > > Now the changes have been made to calculate the rate and register > values from alpha_width instead hardcoding it so that it can work > for all the cases. > > Signed-off-by: Abhishek Sahu > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project