[v3 RFC 0/2] drm/msm: Add support for Adreno a6xx

[Jordan Crouse <jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]

This is an RFC for the initial version of a6xx support for the Adreno a6xx GPU
family as found on the sdm845 SoC.  This code is ahead of most of the rest of
the sdm845 code that would be needed to actually bring up a device and it is
definitely far in advance of any user side support for the a6xx GPU so this is
mainly just a chance to look over the code structure and get a feel for the
direction that the hardware is going in.

The a6xx GPU is an iteration of the a5xx family so most of the GPU side code
looks pretty close to the same except for the usual register differences. The
big different is in power control.  On the a5xx there was a rudimentary device
called the GMU that did some basic power stuff but left most of the complexity
to the kernel.  On the a6xx the power complexity is being moved to a component
called the GMU (graphics management unit).

The kernel is responsible for powering the GMU and in turn the GMU is
responsible for powering the GPU and handling power collapse and advance power
saving techniques. Of course the devil is in the details and what we save in
power management complexity is unfortunately replaced by the complexity involved
in communicating with and controlling the GMU.

This version stack depends on the following dependencies:

https://patchwork.kernel.org/patch/10286375/ - dev_pm_opp_get_of_node
https://patchwork.kernel.org/patch/10283073/ - command DB driver
https://patchwork.kernel.org/patch/10281613/ - smmu pm_runtime/sleep opps

[v3 - fix inverted register definition for GMU_SPTPRAC_CLK_STATUS; fix incorrect
register check in a5xx_gmu_gx_is_on(), use dev_pm_opp_get_of_node() from
Rajendra and Viresh to read the qcom,level from the device tree; read qcom,level
from the DT to get the voltage level to pass to the GMU, fix issues
identified by smatch]

[v2 - addressed comments from Lucas Stach; added pm_runtime_get_supplier calls
for accesses to the GMU IOMMU; moved to SPDX headers for new files]

Jordan Crouse (1):
  drm/msm: Add A6XX device support

Sharat Masetty (1):
  drm/msm: Add generated headers for A6XX

 drivers/gpu/drm/msm/Makefile               |    3 +
 drivers/gpu/drm/msm/adreno/a6xx.xml.h      | 1600 ++++++++++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c      | 1225 +++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h      |  162 +++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h  |  382 +++++++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c      |  808 ++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h      |   60 ++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c      |  435 ++++++++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h      |  127 +++
 drivers/gpu/drm/msm/adreno/adreno_device.c |   12 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c    |    2 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h    |    5 +-
 drivers/gpu/drm/msm/msm_gpu.c              |    2 +-
 13 files changed, 4820 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.h

-- 
2.16.1

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