Re: [Freedreno] [DPU PATCH 7/7] drm/msm: remove dpu specific uapi header

[Sean Paul <seanpaul@chromium.org>]

On Wed, May 23, 2018 at 12:31:02PM -0700, Jeykumar Sankaran wrote:
> remove unwanted dpu uapi headers exposing custom
> payload layouts for custom properties
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  include/uapi/drm/dpu_drm.h    | 220 ---------------------------
>  include/uapi/drm/msm_drm_pp.h | 345 ------------------------------------------
>  2 files changed, 565 deletions(-)
>  delete mode 100644 include/uapi/drm/dpu_drm.h
>  delete mode 100644 include/uapi/drm/msm_drm_pp.h
> 
> diff --git a/include/uapi/drm/dpu_drm.h b/include/uapi/drm/dpu_drm.h
> deleted file mode 100644
> index 93af1fb..0000000
> --- a/include/uapi/drm/dpu_drm.h
> +++ /dev/null
> @@ -1,220 +0,0 @@
> -#ifndef _DPU_DRM_H_
> -#define _DPU_DRM_H_
> -
> -#include "drm.h"
> -
> -/* Total number of supported color planes */
> -#define DPU_MAX_PLANES  4
> -
> -/* Total number of parameterized detail enhancer mapping curves */
> -#define DPU_MAX_DE_CURVES 3
> -
> - /* Y/RGB and UV filter configuration */
> -#define FILTER_EDGE_DIRECTED_2D		0x0
> -#define FILTER_CIRCULAR_2D		0x1
> -#define FILTER_SEPARABLE_1D		0x2
> -#define FILTER_BILINEAR			0x3
> -
> -/* Alpha filters */
> -#define FILTER_ALPHA_DROP_REPEAT	0x0
> -#define FILTER_ALPHA_BILINEAR		0x1
> -#define FILTER_ALPHA_2D			0x3
> -
> -/* Blend filters */
> -#define FILTER_BLEND_CIRCULAR_2D	0x0
> -#define FILTER_BLEND_SEPARABLE_1D	0x1
> -
> -/* LUT configuration flags */
> -#define SCALER_LUT_SWAP			0x1
> -#define SCALER_LUT_DIR_WR		0x2
> -#define SCALER_LUT_Y_CIR_WR		0x4
> -#define SCALER_LUT_UV_CIR_WR		0x8
> -#define SCALER_LUT_Y_SEP_WR		0x10
> -#define SCALER_LUT_UV_SEP_WR		0x20
> -
> -/**
> - * Blend operations for "blend_op" property
> - *
> - * @DPU_DRM_BLEND_OP_NOT_DEFINED:   No blend operation defined for the layer.
> - * @DPU_DRM_BLEND_OP_OPAQUE:        Apply a constant blend operation. The layer
> - *                                  would appear opaque in case fg plane alpha
> - *                                  is 0xff.
> - * @DPU_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
> - *                                  has alpha pre-multiplication done. If the fg
> - *                                  plane alpha is less than 0xff, apply
> - *                                  modulation as well. This operation is
> - *                                  intended on layers having alpha channel.
> - * @DPU_DRM_BLEND_OP_COVERAGE:      Apply source over blend rule. Layer is not
> - *                                  alpha pre-multiplied. Apply
> - *                                  pre-multiplication. If fg plane alpha is
> - *                                  less than 0xff, apply modulation as well.
> - * @DPU_DRM_BLEND_OP_MAX:           Used to track maximum blend operation
> - *                                  possible by mdp.
> - */
> -#define DPU_DRM_BLEND_OP_NOT_DEFINED    0
> -#define DPU_DRM_BLEND_OP_OPAQUE         1
> -#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
> -#define DPU_DRM_BLEND_OP_COVERAGE       3
> -#define DPU_DRM_BLEND_OP_MAX            4
> -
> -/**
> - * Bit masks for "src_config" property
> - * construct bitmask via (1UL << DPU_DRM_<flag>)
> - */
> -#define DPU_DRM_DEINTERLACE         0   /* Specifies interlaced input */
> -
> -/* DRM bitmasks are restricted to 0..63 */
> -#define DPU_DRM_BITMASK_COUNT       64
> -
> -/* Number of dest scalers supported */
> -#define DPU_MAX_DS_COUNT 2
> -
> -/*
> - * Destination scaler flag config
> - */
> -#define DPU_DRM_DESTSCALER_ENABLE           0x1
> -#define DPU_DRM_DESTSCALER_SCALE_UPDATE     0x2
> -#define DPU_DRM_DESTSCALER_ENHANCER_UPDATE  0x4
> -#define DPU_DRM_DESTSCALER_PU_ENABLE        0x8
> -
> -/**
> - * struct dpu_drm_dest_scaler_cfg - destination scaler config structure
> - * @flags:      Flag to switch between mode for destination scaler
> - *              refer to destination scaler flag config
> - * @index:      Destination scaler selection index
> - * @lm_width:   Layer mixer width configuration
> - * @lm_height:  Layer mixer height configuration
> - * @scaler_cfg: The scaling parameters for all the mode except disable
> - *              Userspace pointer to struct dpu_drm_scaler_v2
> - */
> -struct dpu_drm_dest_scaler_cfg {
> -	uint32_t flags;
> -	uint32_t index;
> -	uint32_t lm_width;
> -	uint32_t lm_height;
> -	uint64_t scaler_cfg;
> -};
> -
> -/**
> - * struct dpu_drm_dest_scaler_data - destination scaler data struct
> - * @num_dest_scaler: Number of dest scalers to be configured
> - * @ds_cfg:          Destination scaler block configuration
> - */
> -struct dpu_drm_dest_scaler_data {
> -	uint32_t num_dest_scaler;
> -	struct dpu_drm_dest_scaler_cfg ds_cfg[DPU_MAX_DS_COUNT];
> -};
> -
> -/*
> - * Define constants for struct dpu_drm_csc
> - */
> -#define DPU_CSC_MATRIX_COEFF_SIZE   9
> -#define DPU_CSC_CLAMP_SIZE          6
> -#define DPU_CSC_BIAS_SIZE           3
> -
> -/**
> - * struct dpu_drm_csc_v1 - version 1 of struct dpu_drm_csc
> - * @ctm_coeff:          Matrix coefficients, in S31.32 format
> - * @pre_bias:           Pre-bias array values
> - * @post_bias:          Post-bias array values
> - * @pre_clamp:          Pre-clamp array values
> - * @post_clamp:         Post-clamp array values
> - */
> -struct dpu_drm_csc_v1 {
> -	int64_t ctm_coeff[DPU_CSC_MATRIX_COEFF_SIZE];
> -	uint32_t pre_bias[DPU_CSC_BIAS_SIZE];
> -	uint32_t post_bias[DPU_CSC_BIAS_SIZE];
> -	uint32_t pre_clamp[DPU_CSC_CLAMP_SIZE];
> -	uint32_t post_clamp[DPU_CSC_CLAMP_SIZE];
> -};
> -
> -/**
> - * struct dpu_drm_color - struct to store the color and alpha values
> - * @color_0: Color 0 value
> - * @color_1: Color 1 value
> - * @color_2: Color 2 value
> - * @color_3: Color 3 value
> - */
> -struct dpu_drm_color {
> -	uint32_t color_0;
> -	uint32_t color_1;
> -	uint32_t color_2;
> -	uint32_t color_3;
> -};
> -
> -/* Total number of supported dim layers */
> -#define DPU_MAX_DIM_LAYERS 7
> -
> -/* DPU_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */
> -/* Color fill inside of the rect, including border */
> -#define DPU_DRM_DIM_LAYER_INCLUSIVE     0x1
> -/* Color fill outside of the rect, excluding border */
> -#define DPU_DRM_DIM_LAYER_EXCLUSIVE     0x2
> -
> -/**
> - * struct dpu_drm_dim_layer - dim layer cfg struct
> - * @flags:         Refer DPU_DRM_DIM_LAYER_CONFIG_FLAG for possible values
> - * @stage:         Blending stage of the dim layer
> - * @color_fill:    Color fill for dim layer
> - * @rect:          Dim layer coordinates
> - */
> -struct dpu_drm_dim_layer_cfg {
> -	uint32_t flags;
> -	uint32_t stage;
> -	struct dpu_drm_color color_fill;
> -	struct drm_clip_rect rect;
> -};
> -
> -/**
> - * struct dpu_drm_dim_layer_v1 - version 1 of dim layer struct
> - * @num_layers:    Numer of Dim Layers
> - * @layer:         Dim layer user cfgs ptr for the num_layers
> - */
> -struct dpu_drm_dim_layer_v1 {
> -	uint32_t num_layers;
> -	struct dpu_drm_dim_layer_cfg layer_cfg[DPU_MAX_DIM_LAYERS];
> -};
> -
> -/* Writeback Config version definition */
> -#define DPU_DRM_WB_CFG		0x1
> -
> -/* DPU_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */
> -#define DPU_DRM_WB_CFG_FLAGS_CONNECTED	(1<<0)
> -
> -/**
> - * struct dpu_drm_wb_cfg - Writeback configuration structure
> - * @flags:		see DRM_MSM_WB_CONFIG_FLAGS
> - * @connector_id:	writeback connector identifier
> - * @count_modes:	Count of modes in modes_ptr
> - * @modes:		Pointer to struct drm_mode_modeinfo
> - */
> -struct dpu_drm_wb_cfg {
> -	uint32_t flags;
> -	uint32_t connector_id;
> -	uint32_t count_modes;
> -	uint64_t modes;
> -};
> -
> -#define DPU_MAX_ROI_V1	4
> -
> -/**
> - * struct dpu_drm_roi_v1 - list of regions of interest for a drm object
> - * @num_rects: number of valid rectangles in the roi array
> - * @roi: list of roi rectangles
> - */
> -struct dpu_drm_roi_v1 {
> -	uint32_t num_rects;
> -	struct drm_clip_rect roi[DPU_MAX_ROI_V1];
> -};
> -
> -/**
> - * Define extended power modes supported by the DPU connectors.
> - */
> -#define DPU_MODE_DPMS_ON	0
> -#define DPU_MODE_DPMS_LP1	1
> -#define DPU_MODE_DPMS_LP2	2
> -#define DPU_MODE_DPMS_STANDBY	3
> -#define DPU_MODE_DPMS_SUSPEND	4
> -#define DPU_MODE_DPMS_OFF	5
> -
> -#endif /* _DPU_DRM_H_ */
> diff --git a/include/uapi/drm/msm_drm_pp.h b/include/uapi/drm/msm_drm_pp.h
> deleted file mode 100644
> index a3b5794..0000000
> --- a/include/uapi/drm/msm_drm_pp.h
> +++ /dev/null
> @@ -1,345 +0,0 @@
> -#ifndef _MSM_DRM_PP_H_
> -#define _MSM_DRM_PP_H_
> -
> -#include <linux/types.h>
> -/**
> - * struct drm_msm_pcc_coeff - PCC coefficient structure for each color
> - *                            component.
> - * @c: constant coefficient.
> - * @r: red coefficient.
> - * @g: green coefficient.
> - * @b: blue coefficient.
> - * @rg: red green coefficient.
> - * @gb: green blue coefficient.
> - * @rb: red blue coefficient.
> - * @rgb: red blue green coefficient.
> - */
> -
> -struct drm_msm_pcc_coeff {
> -	__u32 c;
> -	__u32 r;
> -	__u32 g;
> -	__u32 b;
> -	__u32 rg;
> -	__u32 gb;
> -	__u32 rb;
> -	__u32 rgb;
> -};
> -
> -/**
> - * struct drm_msm_pcc - pcc feature structure
> - * @flags: for customizing operations
> - * @r: red coefficients.
> - * @g: green coefficients.
> - * @b: blue coefficients.
> - * @r_rr: second order coefficients
> - * @r_gg: second order coefficients
> - * @r_bb: second order coefficients
> - * @g_rr: second order coefficients
> - * @g_gg: second order coefficients
> - * @g_bb: second order coefficients
> - * @b_rr: second order coefficients
> - * @b_gg: second order coefficients
> - * @b_bb: second order coefficients
> - */
> -#define DRM_MSM_PCC3
> -struct drm_msm_pcc {
> -	__u64 flags;
> -	struct drm_msm_pcc_coeff r;
> -	struct drm_msm_pcc_coeff g;
> -	struct drm_msm_pcc_coeff b;
> -	__u32 r_rr;
> -	__u32 r_gg;
> -	__u32 r_bb;
> -	__u32 g_rr;
> -	__u32 g_gg;
> -	__u32 g_bb;
> -	__u32 b_rr;
> -	__u32 b_gg;
> -	__u32 b_bb;
> -};
> -
> -/* struct drm_msm_pa_vlut - picture adjustment vLUT structure
> - * flags: for customizing vlut operation
> - * val: vLUT values
> - */
> -#define PA_VLUT_SIZE 256
> -struct drm_msm_pa_vlut {
> -	__u64 flags;
> -	__u32 val[PA_VLUT_SIZE];
> -};
> -
> -/* struct drm_msm_memcol - Memory color feature structure.
> - *                         Skin, sky, foliage features are supported.
> - * @prot_flags: Bit mask for enabling protection feature.
> - * @color_adjust_p0: Adjustment curve.
> - * @color_adjust_p1: Adjustment curve.
> - * @color_adjust_p2: Adjustment curve.
> - * @blend_gain: Blend gain weightage from othe PA features.
> - * @sat_hold: Saturation hold value.
> - * @val_hold: Value hold info.
> - * @hue_region: Hue qualifier.
> - * @sat_region: Saturation qualifier.
> - * @val_region: Value qualifier.
> - */
> -#define DRM_MSM_MEMCOL
> -struct drm_msm_memcol {
> -	__u64 prot_flags;
> -	__u32 color_adjust_p0;
> -	__u32 color_adjust_p1;
> -	__u32 color_adjust_p2;
> -	__u32 blend_gain;
> -	__u32 sat_hold;
> -	__u32 val_hold;
> -	__u32 hue_region;
> -	__u32 sat_region;
> -	__u32 val_region;
> -};
> -
> -#define GAMUT_3D_MODE_17 1
> -#define GAMUT_3D_MODE_5 2
> -#define GAMUT_3D_MODE_13 3
> -
> -#define GAMUT_3D_MODE17_TBL_SZ 1229
> -#define GAMUT_3D_MODE5_TBL_SZ 32
> -#define GAMUT_3D_MODE13_TBL_SZ 550
> -#define GAMUT_3D_SCALE_OFF_SZ 16
> -#define GAMUT_3D_SCALEB_OFF_SZ 12
> -#define GAMUT_3D_TBL_NUM 4
> -#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
> -#define GAMUT_3D_MAP_EN (1 << 0)
> -
> -/**
> - * struct drm_msm_3d_col - 3d gamut color component structure
> - * @c0: Holds c0 value
> - * @c2_c1: Holds c2/c1 values
> - */
> -struct drm_msm_3d_col {
> -	__u32 c2_c1;
> -	__u32 c0;
> -};
> -/**
> - * struct drm_msm_3d_gamut - 3d gamut feature structure
> - * @flags: flags for the feature values are:
> - *         0 - no map
> - *         GAMUT_3D_MAP_EN - enable map
> - * @mode: lut mode can take following values:
> - *        - GAMUT_3D_MODE_17
> - *        - GAMUT_3D_MODE_5
> - *        - GAMUT_3D_MODE_13
> - * @scale_off: Scale offset table
> - * @col: Color component tables
> - */
> -struct drm_msm_3d_gamut {
> -	__u64 flags;
> -	__u32 mode;
> -	__u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
> -	struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
> -};
> -
> -#define PGC_TBL_LEN 512
> -#define PGC_8B_ROUND (1 << 0)
> -/**
> - * struct drm_msm_pgc_lut - pgc lut feature structure
> - * @flags: flags for the featue values can be:
> - *         - PGC_8B_ROUND
> - * @c0: color0 component lut
> - * @c1: color1 component lut
> - * @c2: color2 component lut
> - */
> -struct drm_msm_pgc_lut {
> -	__u64 flags;
> -	__u32 c0[PGC_TBL_LEN];
> -	__u32 c1[PGC_TBL_LEN];
> -	__u32 c2[PGC_TBL_LEN];
> -};
> -
> -#define IGC_TBL_LEN 256
> -#define IGC_DITHER_ENABLE (1 << 0)
> -/**
> - * struct drm_msm_igc_lut - igc lut feature structure
> - * @flags: flags for the feature customization, values can be:
> - *             - IGC_DITHER_ENABLE: Enable dither functionality
> - * @c0: color0 component lut
> - * @c1: color1 component lut
> - * @c2: color2 component lut
> - * @strength: dither strength, considered valid when IGC_DITHER_ENABLE
> - *            is set in flags. Strength value based on source bit width.
> - */
> -struct drm_msm_igc_lut {
> -	__u64 flags;
> -	__u32 c0[IGC_TBL_LEN];
> -	__u32 c1[IGC_TBL_LEN];
> -	__u32 c2[IGC_TBL_LEN];
> -	__u32 strength;
> -};
> -
> -#define AD4_LUT_GRP0_SIZE 33
> -#define AD4_LUT_GRP1_SIZE 32
> -/*
> - * struct drm_msm_ad4_init - ad4 init structure set by user-space client.
> - *                           Init param values can change based on tuning
> - *                           hence it is passed by user-space clients.
> - */
> -struct drm_msm_ad4_init {
> -	__u32 init_param_001[AD4_LUT_GRP0_SIZE];
> -	__u32 init_param_002[AD4_LUT_GRP0_SIZE];
> -	__u32 init_param_003[AD4_LUT_GRP0_SIZE];
> -	__u32 init_param_004[AD4_LUT_GRP0_SIZE];
> -	__u32 init_param_005[AD4_LUT_GRP1_SIZE];
> -	__u32 init_param_006[AD4_LUT_GRP1_SIZE];
> -	__u32 init_param_007[AD4_LUT_GRP0_SIZE];
> -	__u32 init_param_008[AD4_LUT_GRP0_SIZE];
> -	__u32 init_param_009;
> -	__u32 init_param_010;
> -	__u32 init_param_011;
> -	__u32 init_param_012;
> -	__u32 init_param_013;
> -	__u32 init_param_014;
> -	__u32 init_param_015;
> -	__u32 init_param_016;
> -	__u32 init_param_017;
> -	__u32 init_param_018;
> -	__u32 init_param_019;
> -	__u32 init_param_020;
> -	__u32 init_param_021;
> -	__u32 init_param_022;
> -	__u32 init_param_023;
> -	__u32 init_param_024;
> -	__u32 init_param_025;
> -	__u32 init_param_026;
> -	__u32 init_param_027;
> -	__u32 init_param_028;
> -	__u32 init_param_029;
> -	__u32 init_param_030;
> -	__u32 init_param_031;
> -	__u32 init_param_032;
> -	__u32 init_param_033;
> -	__u32 init_param_034;
> -	__u32 init_param_035;
> -	__u32 init_param_036;
> -	__u32 init_param_037;
> -	__u32 init_param_038;
> -	__u32 init_param_039;
> -	__u32 init_param_040;
> -	__u32 init_param_041;
> -	__u32 init_param_042;
> -	__u32 init_param_043;
> -	__u32 init_param_044;
> -	__u32 init_param_045;
> -	__u32 init_param_046;
> -	__u32 init_param_047;
> -	__u32 init_param_048;
> -	__u32 init_param_049;
> -	__u32 init_param_050;
> -	__u32 init_param_051;
> -	__u32 init_param_052;
> -	__u32 init_param_053;
> -	__u32 init_param_054;
> -	__u32 init_param_055;
> -	__u32 init_param_056;
> -	__u32 init_param_057;
> -	__u32 init_param_058;
> -	__u32 init_param_059;
> -	__u32 init_param_060;
> -	__u32 init_param_061;
> -	__u32 init_param_062;
> -	__u32 init_param_063;
> -	__u32 init_param_064;
> -	__u32 init_param_065;
> -	__u32 init_param_066;
> -	__u32 init_param_067;
> -	__u32 init_param_068;
> -	__u32 init_param_069;
> -	__u32 init_param_070;
> -	__u32 init_param_071;
> -	__u32 init_param_072;
> -	__u32 init_param_073;
> -	__u32 init_param_074;
> -	__u32 init_param_075;
> -};
> -
> -/*
> - * struct drm_msm_ad4_cfg - ad4 config structure set by user-space client.
> - *                           Config param values can vary based on tuning,
> - *                           hence it is passed by user-space clients.
> - */
> -struct drm_msm_ad4_cfg {
> -	__u32 cfg_param_001;
> -	__u32 cfg_param_002;
> -	__u32 cfg_param_003;
> -	__u32 cfg_param_004;
> -	__u32 cfg_param_005;
> -	__u32 cfg_param_006;
> -	__u32 cfg_param_007;
> -	__u32 cfg_param_008;
> -	__u32 cfg_param_009;
> -	__u32 cfg_param_010;
> -	__u32 cfg_param_011;
> -	__u32 cfg_param_012;
> -	__u32 cfg_param_013;
> -	__u32 cfg_param_014;
> -	__u32 cfg_param_015;
> -	__u32 cfg_param_016;
> -	__u32 cfg_param_017;
> -	__u32 cfg_param_018;
> -	__u32 cfg_param_019;
> -	__u32 cfg_param_020;
> -	__u32 cfg_param_021;
> -	__u32 cfg_param_022;
> -	__u32 cfg_param_023;
> -	__u32 cfg_param_024;
> -	__u32 cfg_param_025;
> -	__u32 cfg_param_026;
> -	__u32 cfg_param_027;
> -	__u32 cfg_param_028;
> -	__u32 cfg_param_029;
> -	__u32 cfg_param_030;
> -	__u32 cfg_param_031;
> -	__u32 cfg_param_032;
> -	__u32 cfg_param_033;
> -	__u32 cfg_param_034;
> -	__u32 cfg_param_035;
> -	__u32 cfg_param_036;
> -	__u32 cfg_param_037;
> -	__u32 cfg_param_038;
> -	__u32 cfg_param_039;
> -	__u32 cfg_param_040;
> -	__u32 cfg_param_041;
> -	__u32 cfg_param_042;
> -	__u32 cfg_param_043;
> -	__u32 cfg_param_044;
> -	__u32 cfg_param_045;
> -	__u32 cfg_param_046;
> -	__u32 cfg_param_047;
> -	__u32 cfg_param_048;
> -	__u32 cfg_param_049;
> -	__u32 cfg_param_050;
> -	__u32 cfg_param_051;
> -	__u32 cfg_param_052;
> -	__u32 cfg_param_053;
> -};
> -
> -#define DITHER_MATRIX_SZ 16
> -
> -/**
> - * struct drm_msm_dither - dither feature structure
> - * @flags: for customizing operations
> - * @temporal_en: temperal dither enable
> - * @c0_bitdepth: c0 component bit depth
> - * @c1_bitdepth: c1 component bit depth
> - * @c2_bitdepth: c2 component bit depth
> - * @c3_bitdepth: c2 component bit depth
> - * @matrix: dither strength matrix
> - */
> -struct drm_msm_dither {
> -	__u64 flags;
> -	__u32 temporal_en;
> -	__u32 c0_bitdepth;
> -	__u32 c1_bitdepth;
> -	__u32 c2_bitdepth;
> -	__u32 c3_bitdepth;
> -	__u32 matrix[DITHER_MATRIX_SZ];
> -};
> -
> -#endif /* _MSM_DRM_PP_H_ */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
> _______________________________________________
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> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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