From: Sean Paul <seanpaul@chromium.org>
To: abhinavk@codeaurora.org, architt@codeaurora.org,
chandanu@codeaurora.org, jsanka@codeaurora.org,
jcrouse@codeaurora.org, ryadav@codeaurora.org,
seanpaul@chromium.org, skolluku@codeaurora.org,
dri-devel@lists.freedesktop.org, robdclark@gmail.com,
airlied@linux.ie, freedreno@lists.freedesktop.org,
linux-arm-msm@vger.kernel.org, nganji@codeaurora.org,
hoegsberg@chromium.org, dovizu@chromium.org, robh+dt@kernel.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
Lloyd Atkinson <latkinso@codeaurora.org>,
Daniel Mack <daniel@zonque.org>,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 05/21] drm/msm/dsi: adjust dsi timing for dual dsi mode
Date: Mon, 9 Jul 2018 13:31:41 -0400 [thread overview]
Message-ID: <20180709173200.238457-6-seanpaul@chromium.org> (raw)
In-Reply-To: <20180709173200.238457-1-seanpaul@chromium.org>
From: Chandan Uddaraju <chandanu@codeaurora.org>
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Changes in V2:
--Removed Change-Id from the commit text tags.
Changes in V3:
--Instead of adjusting the DRM mode structure, divide
the clocks and horizontal timings in DSI host just
before configuring the values.
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 ++-
drivers/gpu/drm/msm/dsi/dsi_host.c | 55 +++++++++++++++++++++------
drivers/gpu/drm/msm/dsi/dsi_manager.c | 7 ++--
3 files changed, 52 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 70d9a9a47acd..01c38f67d699 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -162,7 +162,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host,
int msm_dsi_host_enable(struct mipi_dsi_host *host);
int msm_dsi_host_disable(struct mipi_dsi_host *host);
int msm_dsi_host_power_on(struct mipi_dsi_host *host,
- struct msm_dsi_phy_shared_timings *phy_shared_timings);
+ struct msm_dsi_phy_shared_timings *phy_shared_timings,
+ bool is_dual_dsi);
int msm_dsi_host_power_off(struct mipi_dsi_host *host);
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode);
@@ -175,7 +176,8 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
- struct msm_dsi_phy_clk_request *clk_req);
+ struct msm_dsi_phy_clk_request *clk_req,
+ bool is_dual_dsi);
void msm_dsi_host_destroy(struct mipi_dsi_host *host);
int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 2f1a2780658a..671039b7b75b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -118,6 +118,7 @@ struct msm_dsi_host {
struct clk *byte_intf_clk;
u32 byte_clk_rate;
+ u32 pixel_clk_rate;
u32 esc_clk_rate;
/* DSI v2 specific clocks */
@@ -511,7 +512,7 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
goto error;
}
- ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -592,7 +593,7 @@ static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
goto error;
}
- ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -662,7 +663,7 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
}
}
-static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
+static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
@@ -676,14 +677,28 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
}
pclk_rate = mode->clock * 1000;
+
+ /*
+ * For dual DSI mode, the current DRM mode has
+ * the complete width of the panel. Since, the complete
+ * panel is driven by two DSI controllers, the
+ * the clock rates have to be split between
+ * the two dsi controllers. Adjust the byte and
+ * pixel clock rates for each dsi host accordingly.
+ */
+ if (is_dual_dsi)
+ pclk_rate /= 2;
+
if (lanes > 0) {
msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
}
+ msm_host->pixel_clk_rate = pclk_rate;
- DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+ DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
+ msm_host->byte_clk_rate);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
@@ -885,7 +900,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
dsi_write(msm_host, REG_DSI_CTRL, data);
}
-static void dsi_timing_setup(struct msm_dsi_host *msm_host)
+static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
@@ -897,10 +912,26 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host)
u32 ha_end = ha_start + mode->hdisplay;
u32 va_start = v_total - mode->vsync_start;
u32 va_end = va_start + mode->vdisplay;
+ u32 hdisplay = mode->hdisplay;
u32 wc;
DBG("");
+ /*
+ * For dual DSI mode, the current DRM mode has
+ * the complete width of the panel. Since, the complete
+ * panel is driven by two DSI controllers, the horizontal
+ * timings have to be split between the two dsi controllers.
+ * Adjust the DSI host timing values accordingly.
+ */
+ if (is_dual_dsi) {
+ h_total /= 2;
+ hs_end /= 2;
+ ha_start /= 2;
+ ha_end /= 2;
+ hdisplay /= 2;
+ }
+
if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
dsi_write(msm_host, REG_DSI_ACTIVE_H,
DSI_ACTIVE_H_START(ha_start) |
@@ -921,7 +952,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host)
DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
} else { /* command mode */
/* image data and 1 byte write_memory_start cmd */
- wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
@@ -931,7 +962,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host)
MIPI_DSI_DCS_LONG_WRITE));
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
- DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
+ DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) |
DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
}
}
@@ -2189,12 +2220,13 @@ void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
}
void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
- struct msm_dsi_phy_clk_request *clk_req)
+ struct msm_dsi_phy_clk_request *clk_req,
+ bool is_dual_dsi)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
int ret;
- ret = dsi_calc_clk_rate(msm_host);
+ ret = dsi_calc_clk_rate(msm_host, is_dual_dsi);
if (ret) {
pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
return;
@@ -2256,7 +2288,8 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
}
int msm_dsi_host_power_on(struct mipi_dsi_host *host,
- struct msm_dsi_phy_shared_timings *phy_shared_timings)
+ struct msm_dsi_phy_shared_timings *phy_shared_timings,
+ bool is_dual_dsi)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
int ret = 0;
@@ -2291,7 +2324,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
goto fail_disable_clk;
}
- dsi_timing_setup(msm_host);
+ dsi_timing_setup(msm_host, is_dual_dsi);
dsi_sw_reset(msm_host);
dsi_ctrl_config(msm_host, true, phy_shared_timings);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 4cb1cb68878b..3bb506b44a4b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -134,8 +134,9 @@ static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
{
struct msm_dsi_phy_clk_request clk_req;
int ret;
+ bool is_dual_dsi = IS_DUAL_DSI();
- msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req);
+ msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);
ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);
msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
@@ -458,7 +459,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
if (is_dual_dsi && (DSI_1 == id))
return;
- ret = msm_dsi_host_power_on(host, &phy_shared_timings[id]);
+ ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi);
if (ret) {
pr_err("%s: power on host %d failed, %d\n", __func__, id, ret);
goto host_on_fail;
@@ -466,7 +467,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
if (is_dual_dsi && msm_dsi1) {
ret = msm_dsi_host_power_on(msm_dsi1->host,
- &phy_shared_timings[DSI_1]);
+ &phy_shared_timings[DSI_1], is_dual_dsi);
if (ret) {
pr_err("%s: power on host1 failed, %d\n",
__func__, ret);
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2018-07-09 17:31 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-09 17:31 [PATCH 00/21] drm/msm: Add support for SDM845 Display Processing Unit (DPU) Sean Paul
2018-07-09 17:31 ` [PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding Sean Paul
[not found] ` <20180709173200.238457-2-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-20 14:13 ` Rob Herring
2018-07-09 17:31 ` Sean Paul [this message]
[not found] ` <20180709173200.238457-6-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 14:17 ` [PATCH 05/21] drm/msm/dsi: adjust dsi timing for dual dsi mode Archit Taneja
2018-07-09 17:31 ` [PATCH 06/21] drm/msm/dsi: Use one connector for dual DSI mode Sean Paul
[not found] ` <20180709173200.238457-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-09 17:31 ` [PATCH 02/21] dt-bindings: clock: Introduce QCOM Display clock bindings Sean Paul
2018-07-09 17:31 ` [PATCH 03/21] drm: Add support for pps and compression mode command packet Sean Paul
2018-07-09 17:31 ` [PATCH 04/21] drm: add msm compressed format modifiers Sean Paul
[not found] ` <20180709173200.238457-5-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 12:28 ` Rob Clark
2018-07-09 17:31 ` [PATCH 07/21] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll Sean Paul
[not found] ` <20180709173200.238457-8-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 14:28 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 08/21] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks Sean Paul
2018-07-09 17:31 ` [PATCH 09/21] drm/msm/mdp5: subclass msm_mdss for mdp5 Sean Paul
[not found] ` <20180709173200.238457-10-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 14:40 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 10/21] drm/msm: enable zpos normalization Sean Paul
2018-07-09 17:31 ` [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Sean Paul
2018-07-16 14:46 ` Archit Taneja
2018-07-09 17:31 ` [PATCH 12/21] drm/msm: Clean up dangling atomic_wq Sean Paul
2018-07-09 17:31 ` [PATCH 13/21] drm/msm: #define MDP version numbers Sean Paul
2018-07-09 17:31 ` [PATCH 14/21] drm/msm: Use labels for unwinding in the error path Sean Paul
2018-07-09 17:31 ` [PATCH 15/21] drm/msm: #define MAX_<OBJECT> in msm_drv.h Sean Paul
2018-07-09 17:31 ` [PATCH 16/21] drm/msm: Add .commit() callback to msm_kms functions Sean Paul
2018-07-09 17:31 ` [PATCH 18/21] drm/msm: Add pm_suspend/resume callbacks to msm_kms Sean Paul
2018-07-09 17:31 ` [PATCH 20/21] drm/msm: Add SDM845 DPU support Sean Paul
2018-07-09 17:31 ` [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file Sean Paul
2018-07-09 18:07 ` Rob Herring
2018-07-09 18:35 ` Sean Paul
2018-07-09 19:03 ` Rob Clark
2018-07-12 21:13 ` [PATCH v2 " Sean Paul
2018-07-09 17:31 ` [PATCH 17/21] drm/msm: Add preclose kms hook Sean Paul
2018-07-09 17:31 ` [PATCH 19/21] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
[not found] ` <20180709173200.238457-20-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-12 21:08 ` [PATCH v2 " Sean Paul
[not found] ` <20180712210849.146638-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-16 16:21 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180709173200.238457-6-seanpaul@chromium.org \
--to=seanpaul@chromium.org \
--cc=abhinavk@codeaurora.org \
--cc=airlied@linux.ie \
--cc=architt@codeaurora.org \
--cc=chandanu@codeaurora.org \
--cc=daniel.vetter@ffwll.ch \
--cc=daniel@zonque.org \
--cc=dovizu@chromium.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=hoegsberg@chromium.org \
--cc=jcrouse@codeaurora.org \
--cc=jsanka@codeaurora.org \
--cc=latkinso@codeaurora.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=narmstrong@baylibre.com \
--cc=nganji@codeaurora.org \
--cc=robdclark@gmail.com \
--cc=robh+dt@kernel.org \
--cc=ryadav@codeaurora.org \
--cc=skolluku@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).