* [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
@ 2018-07-20 20:42 ` Sean Paul
2018-07-20 20:42 ` [PATCH v3 02/19] drm: Add support for pps and compression mode command packet Sean Paul
` (12 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:42 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
From: Jeykumar Sankaran <jsanka@codeaurora.org>
Adds mdp transfer time to msm dsi binding
Changes in v3:
- Added Rob's R-b
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
.../devicetree/bindings/display/msm/dsi.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index 518e9cdf0d4b..d22237a88eae 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -121,6 +121,20 @@ Required properties:
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
regulator is wanted.
+- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
+ panels in microseconds. Driver uses this number to adjust
+ the clock rate according to the expected transfer time.
+ Increasing this value would slow down the mdp processing
+ and can result in slower performance.
+ Decreasing this value can speed up the mdp processing,
+ but this can also impact power consumption.
+ As a rule this time should not be higher than the time
+ that would be expected with the processing at the
+ dsi link rate since anyways this would be the maximum
+ transfer time that could be achieved.
+ If ping pong split is enabled, this time should not be higher
+ than two times the dsi link rate time.
+ If the property is not specified, then the default value is 14000 us.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
@@ -171,6 +185,8 @@ Example:
qcom,master-dsi;
qcom,sync-dual-dsi;
+ qcom,mdss-mdp-transfer-time-us = <12000>;
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dsi_active>;
pinctrl-1 = <&dsi_suspend>;
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 02/19] drm: Add support for pps and compression mode command packet
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-20 20:42 ` [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding Sean Paul
@ 2018-07-20 20:42 ` Sean Paul
2018-07-20 20:42 ` [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode Sean Paul
` (11 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:42 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: linux-fbdev-u79uwXL29TY76Z2rM5mHXA, Bartlomiej Zolnierkiewicz,
Gustavo Padovan, Maarten Lankhorst,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Tomi Valkeinen, vkorjani,
Jean-Christophe Plagniol-Villard
From: vkorjani <vikas.korjani@intel.com>
After enabling DSC we need to send compression mode command packet
and pps data packet, for which 2 new data types are added
07h Compression Mode Data Type Write , short write, 2 parameters
0Ah PPS Long Write (word count determines number of bytes)
This patch adds support to send these packets.
Cc: David Airlie <airlied@linux.ie>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-fbdev@vger.kernel.org
Changes in v3:
- None
Signed-off-by: vkorjani <vikas.korjani@intel.com>
[seanpaul removed pps_write_buffer fn, added types to packet_format helpers]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index bc73b7f5b9fc..80b75501f5c6 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -392,6 +392,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
+ case MIPI_DSI_DCS_COMPRESSION_MODE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -410,6 +411,7 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
bool mipi_dsi_packet_format_is_long(u8 type)
{
switch (type) {
+ case MIPI_DSI_PPS_LONG_WRITE:
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
case MIPI_DSI_GENERIC_LONG_WRITE:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 19aa65a35546..49a53ef8da96 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -38,6 +38,9 @@ enum {
MIPI_DSI_DCS_READ = 0x06,
+ MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
+ MIPI_DSI_PPS_LONG_WRITE = 0x0A,
+
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
MIPI_DSI_END_OF_TRANSMISSION = 0x08,
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-20 20:42 ` [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding Sean Paul
2018-07-20 20:42 ` [PATCH v3 02/19] drm: Add support for pps and compression mode command packet Sean Paul
@ 2018-07-20 20:42 ` Sean Paul
2018-07-20 20:42 ` [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly Sean Paul
` (10 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:42 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: Neil Armstrong, Daniel Vetter, Lloyd Atkinson,
Gustavo A. R. Silva, Sibi Sankar, Shawn Guo
From: Chandan Uddaraju <chandanu@codeaurora.org>
Current DSI driver uses two connectors for dual DSI case even
though we only have one panel. Fix this by implementing one
connector/bridge for dual DSI use case. Use master DSI
controllers to register one connector/bridge.
Changes in v3:
- None
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
[seanpaul removed unused local var causing a build warning]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/dsi/dsi.c | 3 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_manager.c | 112 ++++++--------------------
3 files changed, 30 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index b744bcc7d8ad..ff8164cc6738 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -208,6 +208,9 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
goto fail;
}
+ if (!msm_dsi_manager_validate_current_config(msm_dsi->id))
+ goto fail;
+
msm_dsi->encoder = encoder;
msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id);
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index d3f613c76ffa..08f3fc6771b7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -100,6 +100,7 @@ bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
+bool msm_dsi_manager_validate_current_config(u8 id);
/* msm dsi */
static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 3bb506b44a4b..000721fe5ab4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -306,102 +306,25 @@ static void dsi_mgr_connector_destroy(struct drm_connector *connector)
kfree(dsi_connector);
}
-static void dsi_dual_connector_fix_modes(struct drm_connector *connector)
-{
- struct drm_display_mode *mode, *m;
-
- /* Only support left-right mode */
- list_for_each_entry_safe(mode, m, &connector->probed_modes, head) {
- mode->clock >>= 1;
- mode->hdisplay >>= 1;
- mode->hsync_start >>= 1;
- mode->hsync_end >>= 1;
- mode->htotal >>= 1;
- drm_mode_set_name(mode);
- }
-}
-
-static int dsi_dual_connector_tile_init(
- struct drm_connector *connector, int id)
-{
- struct drm_display_mode *mode;
- /* Fake topology id */
- char topo_id[8] = {'M', 'S', 'M', 'D', 'U', 'D', 'S', 'I'};
-
- if (connector->tile_group) {
- DBG("Tile property has been initialized");
- return 0;
- }
-
- /* Use the first mode only for now */
- mode = list_first_entry(&connector->probed_modes,
- struct drm_display_mode,
- head);
- if (!mode)
- return -EINVAL;
-
- connector->tile_group = drm_mode_get_tile_group(
- connector->dev, topo_id);
- if (!connector->tile_group)
- connector->tile_group = drm_mode_create_tile_group(
- connector->dev, topo_id);
- if (!connector->tile_group) {
- pr_err("%s: failed to create tile group\n", __func__);
- return -ENOMEM;
- }
-
- connector->has_tile = true;
- connector->tile_is_single_monitor = true;
-
- /* mode has been fixed */
- connector->tile_h_size = mode->hdisplay;
- connector->tile_v_size = mode->vdisplay;
-
- /* Only support left-right mode */
- connector->num_h_tile = 2;
- connector->num_v_tile = 1;
-
- connector->tile_v_loc = 0;
- connector->tile_h_loc = (id == DSI_RIGHT) ? 1 : 0;
-
- return 0;
-}
-
static int dsi_mgr_connector_get_modes(struct drm_connector *connector)
{
int id = dsi_mgr_connector_get_id(connector);
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct drm_panel *panel = msm_dsi->panel;
- int ret, num;
+ int num;
if (!panel)
return 0;
- /* Since we have 2 connectors, but only 1 drm_panel in dual DSI mode,
- * panel should not attach to any connector.
- * Only temporarily attach panel to the current connector here,
- * to let panel set mode to this connector.
+ /*
+ * In dual DSI mode, we have one connector that can be
+ * attached to the drm_panel.
*/
drm_panel_attach(panel, connector);
num = drm_panel_get_modes(panel);
- drm_panel_detach(panel);
if (!num)
return 0;
- if (IS_DUAL_DSI()) {
- /* report half resolution to user */
- dsi_dual_connector_fix_modes(connector);
- ret = dsi_dual_connector_tile_init(connector, id);
- if (ret)
- return ret;
- ret = drm_mode_connector_set_tile_property(connector);
- if (ret) {
- pr_err("%s: set tile property failed, %d\n",
- __func__, ret);
- return ret;
- }
- }
-
return num;
}
@@ -455,8 +378,8 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
if (ret)
goto phy_en_fail;
- /* Do nothing with the host if it is DSI 1 in case of dual DSI */
- if (is_dual_dsi && (DSI_1 == id))
+ /* Do nothing with the host if it is slave-DSI in case of dual DSI */
+ if (is_dual_dsi && !IS_MASTER_DSI_LINK(id))
return;
ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi);
@@ -557,11 +480,11 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge)
return;
/*
- * Do nothing with the host if it is DSI 1 in case of dual DSI.
+ * Do nothing with the host if it is slave-DSI in case of dual DSI.
* It is safe to call dsi_mgr_phy_disable() here because a single PHY
* won't be diabled until both PHYs request disable.
*/
- if (is_dual_dsi && (DSI_1 == id))
+ if (is_dual_dsi && !IS_MASTER_DSI_LINK(id))
goto disable_phy;
if (panel) {
@@ -622,7 +545,7 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
mode->vsync_end, mode->vtotal,
mode->type, mode->flags);
- if (is_dual_dsi && (DSI_1 == id))
+ if (is_dual_dsi && !IS_MASTER_DSI_LINK(id))
return;
msm_dsi_host_set_display_mode(host, adjusted_mode);
@@ -690,6 +613,23 @@ struct drm_connector *msm_dsi_manager_connector_init(u8 id)
return connector;
}
+bool msm_dsi_manager_validate_current_config(u8 id)
+{
+ bool is_dual_dsi = IS_DUAL_DSI();
+
+ /*
+ * For dual DSI, we only have one drm panel. For this
+ * use case, we register only one bridge/connector.
+ * Skip bridge/connector initialisation if it is
+ * slave-DSI for dual DSI configuration.
+ */
+ if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) {
+ DBG("Skip bridge registration for slave DSI->id: %d\n", id);
+ return false;
+ }
+ return true;
+}
+
/* initialize bridge */
struct drm_bridge *msm_dsi_manager_bridge_init(u8 id)
{
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (2 preceding siblings ...)
2018-07-20 20:42 ` [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode Sean Paul
@ 2018-07-20 20:42 ` Sean Paul
2018-07-20 20:42 ` [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks Sean Paul
` (9 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:42 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: Archit Taneja, Daniel Vetter, Lloyd Atkinson, Shawn Guo,
Neil Armstrong
From: Abhinav Kumar <abhinavk@codeaurora.org>
Currently, DRM bridge for DPU relies on the default video
mode setting to set the encoder mode.
Add an explicit call to set the encoder mode for bridges.
Changes in v3:
- None
Reviewed-by: Archit Taneja <architt@codeauorora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 000721fe5ab4..29025d9b7c62 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -777,6 +777,7 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags)
struct msm_drm_private *priv;
struct msm_kms *kms;
struct drm_encoder *encoder;
+ bool cmd_mode;
/*
* drm_device pointer is assigned to msm_dsi only in the modeset_init
@@ -791,10 +792,11 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags)
priv = dev->dev_private;
kms = priv->kms;
encoder = msm_dsi_get_encoder(msm_dsi);
+ cmd_mode = !(device_flags &
+ MIPI_DSI_MODE_VIDEO);
if (encoder && kms->funcs->set_encoder_mode)
- if (!(device_flags & MIPI_DSI_MODE_VIDEO))
- kms->funcs->set_encoder_mode(kms, encoder, true);
+ kms->funcs->set_encoder_mode(kms, encoder, cmd_mode);
}
int msm_dsi_manager_register(struct msm_dsi *msm_dsi)
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (3 preceding siblings ...)
2018-07-20 20:42 ` [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly Sean Paul
@ 2018-07-20 20:42 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 10/19] drm/msm: enable zpos normalization Sean Paul
` (8 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:42 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: Steve Kowalik, Luis de Bethencourt, Daniel Vetter,
Maarten Lankhorst, Aishwarya Pant, Ingo Molnar
DPU doesn't use this, so push it into the mdp drivers.
Changes in v3:
- None
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 ++
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 ++
drivers/gpu/drm/msm/msm_atomic.c | 2 --
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4b646bf9c214..44d1cda56974 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -125,6 +125,8 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
+ drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state);
+
/* see 119ecb7fd */
for_each_new_crtc_in_state(state, crtc, crtc_state, i)
drm_crtc_vblank_put(crtc);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 6e12e275deba..bddd625ab91b 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -170,6 +170,8 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s
struct device *dev = &mdp5_kms->pdev->dev;
struct mdp5_global_state *global_state;
+ drm_atomic_helper_wait_for_vblanks(mdp5_kms->dev, state);
+
global_state = mdp5_get_existing_global_state(mdp5_kms);
if (mdp5_kms->smp)
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index f0635c3da7f4..e6f1e25c60af 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -75,8 +75,6 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state)
kms->funcs->complete_commit(kms, state);
- drm_atomic_helper_wait_for_vblanks(dev, state);
-
drm_atomic_helper_commit_hw_done(state);
drm_atomic_helper_cleanup_planes(dev, state);
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 10/19] drm/msm: enable zpos normalization
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (4 preceding siblings ...)
2018-07-20 20:42 ` [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Sean Paul
` (7 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
Enable drm core zpos normalization for planes.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/msm_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2608d3f77956..9c760cee5156 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -439,6 +439,9 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
goto fail;
}
+ /* Enable normalization of plane zpos */
+ ddev->mode_config.normalize_zpos = true;
+
if (kms) {
ret = kms->funcs->hw_init(kms);
if (ret) {
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (5 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 10/19] drm/msm: enable zpos normalization Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 13/19] drm/msm: #define MDP version numbers Sean Paul
` (6 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: Sibi Sankar, Stefan Agner
From: Abhinav Kumar <abhinavk@codeaurora.org>
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Changes in v3:
- Converted pclk_rate to u32 (Archit)
- Rebase on dsi cleanup set in msm-next
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index f6c6eddbcec7..dff8e88efb66 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -702,6 +702,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
u32 pclk_rate;
+ u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
@@ -716,13 +717,15 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
if (is_dual_dsi)
pclk_rate /= 2;
+ pclk_bpp = pclk_rate * bpp;
if (lanes > 0) {
- msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+ do_div(pclk_bpp, (8 * lanes));
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
- msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+ do_div(pclk_bpp, 8);
}
msm_host->pixel_clk_rate = pclk_rate;
+ msm_host->byte_clk_rate = pclk_bpp;
DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
msm_host->byte_clk_rate);
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 13/19] drm/msm: #define MDP version numbers
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (6 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path Sean Paul
` (5 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
Useful for incoming DPU support
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[seanpaul split this from the dpu megapatch]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/msm_drv.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index b73acdd52931..67816543a0d7 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -267,6 +267,9 @@ static int msm_drm_uninit(struct device *dev)
return 0;
}
+#define KMS_MDP4 4
+#define KMS_MDP5 5
+
static int get_mdp_ver(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -411,11 +414,11 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
msm_gem_shrinker_init(ddev);
switch (get_mdp_ver(pdev)) {
- case 4:
+ case KMS_MDP4:
kms = mdp4_kms_init(ddev);
priv->kms = kms;
break;
- case 5:
+ case KMS_MDP5:
kms = mdp5_kms_init(ddev);
break;
default:
@@ -1162,8 +1165,8 @@ static int msm_pdev_remove(struct platform_device *pdev)
}
static const struct of_device_id dt_match[] = {
- { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */
- { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */
+ { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
+ { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (7 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 13/19] drm/msm: #define MDP version numbers Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 15/19] drm/msm: #define MAX_<OBJECT> in msm_drv.h Sean Paul
` (4 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
This simplifies cleanup, to make sure nothing drops out in case of
error.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[seanpaul split out of dpu megapatch and renamed labels]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/msm_drv.c | 44 +++++++++++++++++------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 67816543a0d7..8bd9fe831968 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -372,19 +372,16 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
- drm_dev_unref(ddev);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err_unref_drm_dev;
}
ddev->dev_private = priv;
priv->dev = ddev;
ret = mdp5_mdss_init(ddev);
- if (ret) {
- kfree(priv);
- drm_dev_unref(ddev);
- return ret;
- }
+ if (ret)
+ goto err_free_priv;
mdss = priv->mdss;
@@ -399,17 +396,12 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
/* Bind all our sub-components: */
ret = component_bind_all(dev, ddev);
- if (ret) {
- if (mdss && mdss->funcs)
- mdss->funcs->destroy(ddev);
- kfree(priv);
- drm_dev_unref(ddev);
- return ret;
- }
+ if (ret)
+ goto err_destroy_mdss;
ret = msm_init_vram(ddev);
if (ret)
- goto fail;
+ goto err_msm_uninit;
msm_gem_shrinker_init(ddev);
@@ -435,7 +427,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
*/
dev_err(dev, "failed to load kms\n");
ret = PTR_ERR(kms);
- goto fail;
+ goto err_msm_uninit;
}
/* Enable normalization of plane zpos */
@@ -445,7 +437,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
ret = kms->funcs->hw_init(kms);
if (ret) {
dev_err(dev, "kms hw init failed: %d\n", ret);
- goto fail;
+ goto err_msm_uninit;
}
}
@@ -455,7 +447,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
ret = drm_vblank_init(ddev, priv->num_crtcs);
if (ret < 0) {
dev_err(dev, "failed to initialize vblank\n");
- goto fail;
+ goto err_msm_uninit;
}
if (kms) {
@@ -464,13 +456,13 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
pm_runtime_put_sync(dev);
if (ret < 0) {
dev_err(dev, "failed to install IRQ handler\n");
- goto fail;
+ goto err_msm_uninit;
}
}
ret = drm_dev_register(ddev, 0);
if (ret)
- goto fail;
+ goto err_msm_uninit;
drm_mode_config_reset(ddev);
@@ -481,15 +473,23 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
ret = msm_debugfs_late_init(ddev);
if (ret)
- goto fail;
+ goto err_msm_uninit;
drm_kms_helper_poll_init(ddev);
return 0;
-fail:
+err_msm_uninit:
msm_drm_uninit(dev);
return ret;
+err_destroy_mdss:
+ if (mdss && mdss->funcs)
+ mdss->funcs->destroy(ddev);
+err_free_priv:
+ kfree(priv);
+err_unref_drm_dev:
+ drm_dev_unref(ddev);
+ return ret;
}
/*
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 15/19] drm/msm: #define MAX_<OBJECT> in msm_drv.h
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (8 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions Sean Paul
` (3 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
dpu uses these elsewhere in the driver (in addition to increasing
MAX_PLANES, that'll come later), so pull them out into #define.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[seanpaul pulled this out of the dpu megapatch]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/msm_drv.h | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index fa0376b0f42b..3b206ae6423f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -54,6 +54,12 @@ struct msm_fence_context;
struct msm_gem_address_space;
struct msm_gem_vma;
+#define MAX_CRTCS 8
+#define MAX_PLANES 16
+#define MAX_ENCODERS 8
+#define MAX_BRIDGES 8
+#define MAX_CONNECTORS 8
+
struct msm_file_private {
rwlock_t queuelock;
struct list_head submitqueues;
@@ -117,19 +123,19 @@ struct msm_drm_private {
struct workqueue_struct *wq;
unsigned int num_planes;
- struct drm_plane *planes[16];
+ struct drm_plane *planes[MAX_PLANES];
unsigned int num_crtcs;
- struct drm_crtc *crtcs[8];
+ struct drm_crtc *crtcs[MAX_CRTCS];
unsigned int num_encoders;
- struct drm_encoder *encoders[8];
+ struct drm_encoder *encoders[MAX_ENCODERS];
unsigned int num_bridges;
- struct drm_bridge *bridges[8];
+ struct drm_bridge *bridges[MAX_BRIDGES];
unsigned int num_connectors;
- struct drm_connector *connectors[8];
+ struct drm_connector *connectors[MAX_CONNECTORS];
/* Properties */
struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (9 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 15/19] drm/msm: #define MAX_<OBJECT> in msm_drv.h Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms Sean Paul
` (2 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
Called right before wait_for_commit_done() to perform kickoff for
active crtcs.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[seanpaul split this out of the megapatch]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/msm_atomic.c | 5 +++++
drivers/gpu/drm/msm/msm_kms.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index e6f1e25c60af..c1f1779c980f 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -71,6 +71,11 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state)
drm_atomic_helper_commit_modeset_enables(dev, state);
+ if (kms->funcs->commit) {
+ DRM_DEBUG_ATOMIC("triggering commit\n");
+ kms->funcs->commit(kms, state);
+ }
+
msm_atomic_wait_for_commit_done(dev, state);
kms->funcs->complete_commit(kms, state);
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 76c14221ffdf..761bb07cd7bf 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -42,6 +42,7 @@ struct msm_kms_funcs {
void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
/* modeset, bracketing atomic_commit(): */
void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state);
+ void (*commit)(struct msm_kms *kms, struct drm_atomic_state *state);
void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state *state);
/* functions to wait for atomic commit completed on each CRTC */
void (*wait_for_crtc_commit_done)(struct msm_kms *kms,
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (10 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-20 20:43 ` [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
2018-07-20 20:43 ` [PATCH v3 19/19] drm/msm: Add SDM845 DPU support Sean Paul
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
Used by the dpu driver for custom suspend/resume.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
[seanpaul split this out of the megapatch]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/msm_drv.c | 10 ++++++++++
drivers/gpu/drm/msm/msm_kms.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 8bd9fe831968..e79ad74ca98c 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -903,6 +903,11 @@ static int msm_pm_suspend(struct device *dev)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ /* TODO: Use atomic helper suspend/resume */
+ if (kms && kms->funcs && kms->funcs->pm_suspend)
+ return kms->funcs->pm_suspend(dev);
drm_kms_helper_poll_disable(ddev);
@@ -919,6 +924,11 @@ static int msm_pm_resume(struct device *dev)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ /* TODO: Use atomic helper suspend/resume */
+ if (kms && kms->funcs && kms->funcs->pm_resume)
+ return kms->funcs->pm_resume(dev);
drm_atomic_helper_resume(ddev, priv->pm_state);
drm_kms_helper_poll_enable(ddev);
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 761bb07cd7bf..c15de28ae2dd 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -61,6 +61,9 @@ struct msm_kms_funcs {
void (*set_encoder_mode)(struct msm_kms *kms,
struct drm_encoder *encoder,
bool cmd_mode);
+ /* pm suspend/resume hooks */
+ int (*pm_suspend)(struct device *dev);
+ int (*pm_resume)(struct device *dev);
/* cleanup: */
void (*destroy)(struct msm_kms *kms);
#ifdef CONFIG_DEBUG_FS
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (11 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
2018-07-24 23:31 ` Rob Herring
2018-07-20 20:43 ` [PATCH v3 19/19] drm/msm: Add SDM845 DPU support Sean Paul
13 siblings, 1 reply; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
From: Jeykumar Sankaran <jsanka@codeaurora.org>
Adds bindings for Snapdragon 845 display processing unit
Changes in v2:
- Use SoC specific compatibles for mdss and dpu (Rob Herring)
- Use assigned-clocks to set initial clock frequency (Rob Herring)
Changes in v3 (all suggested by Rob Herring):
- Rename mdss_phys to mdss
- Correct description for clocks/assigned-clocks
- Rename mdp_phys to mdp
- Rename vbif_phys to vbif
- Remove redundant interrupt-parent from mdss_mdp
- Fully specify 'ranges' and use relative reg address in mdss_mdp
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
.../devicetree/bindings/display/msm/dpu.txt | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
new file mode 100644
index 000000000000..ad2e8830324e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -0,0 +1,131 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,sdm845-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+ * "mdss"
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required:
+ * "iface"
+ * "bus"
+ * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,sdm845-dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+ * "mdp"
+ * "vbif"
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required.
+ * "bus"
+ * "iface"
+ * "core"
+ * "vsync"
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+ to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ Port 0 -> DPU_INTF1 (DSI1)
+ Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+Example:
+
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0xae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&clock_dispcc 0>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <300000000>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_iommu 0>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xae00000 0xb2008>;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <0 0 300000000 19200000>;
+
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+ };
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU
2018-07-20 20:43 ` [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
@ 2018-07-24 23:31 ` Rob Herring
0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2018-07-24 23:31 UTC (permalink / raw)
To: Sean Paul
Cc: Mark Rutland, devicetree, ryadav, airlied, linux-arm-msm,
dri-devel, abhinavk, skolluku, dovizu, freedreno, hoegsberg,
chandanu
On Fri, Jul 20, 2018 at 04:43:09PM -0400, Sean Paul wrote:
> From: Jeykumar Sankaran <jsanka@codeaurora.org>
>
> Adds bindings for Snapdragon 845 display processing unit
>
> Changes in v2:
> - Use SoC specific compatibles for mdss and dpu (Rob Herring)
> - Use assigned-clocks to set initial clock frequency (Rob Herring)
>
> Changes in v3 (all suggested by Rob Herring):
> - Rename mdss_phys to mdss
> - Correct description for clocks/assigned-clocks
> - Rename mdp_phys to mdp
> - Rename vbif_phys to vbif
> - Remove redundant interrupt-parent from mdss_mdp
> - Fully specify 'ranges' and use relative reg address in mdss_mdp
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
> .../devicetree/bindings/display/msm/dpu.txt | 131 ++++++++++++++++++
> 1 file changed, 131 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 19/19] drm/msm: Add SDM845 DPU support
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
` (12 preceding siblings ...)
2018-07-20 20:43 ` [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
@ 2018-07-20 20:43 ` Sean Paul
13 siblings, 0 replies; 26+ messages in thread
From: Sean Paul @ 2018-07-20 20:43 UTC (permalink / raw)
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ, architt-sgV2jX0FEOL9JmXXK+q4OQ,
chandanu-sgV2jX0FEOL9JmXXK+q4OQ, jsanka-sgV2jX0FEOL9JmXXK+q4OQ,
jcrouse-sgV2jX0FEOL9JmXXK+q4OQ, ryadav-sgV2jX0FEOL9JmXXK+q4OQ,
seanpaul-F7+t8E8rja9g9hUCZPvPmw, skolluku-sgV2jX0FEOL9JmXXK+q4OQ,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
robdclark-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
nganji-sgV2jX0FEOL9JmXXK+q4OQ, hoegsberg-F7+t8E8rja9g9hUCZPvPmw,
dovizu-F7+t8E8rja9g9hUCZPvPmw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
From: Jeykumar Sankaran <jsanka@codeaurora.org>
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 32 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 479 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 637 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 133 +
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2504 ++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 484 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 2393 +++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 103 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2575 +++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 191 ++
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 453 +++
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 905 ++++++
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 922 ++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 1276 ++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 136 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 155 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 53 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 511 ++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 804 +++++
.../drm/msm/disp/dpu1/dpu_hw_catalog_format.h | 182 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 323 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 139 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 540 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 218 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1183 ++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 257 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 349 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 128 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 261 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 122 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 465 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 250 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 136 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 753 +++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 424 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 398 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 202 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 452 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 358 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 275 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h | 128 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 56 +
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 204 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h | 57 +
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 66 +
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h | 59 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1345 +++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 402 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 245 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1963 +++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 175 ++
.../gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 249 ++
.../gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 225 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 1079 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 199 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 1007 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 384 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h | 94 +
.../gpu/drm/msm/disp/dpu1/msm_media_info.h | 1376 +++++++++
drivers/gpu/drm/msm/msm_drv.c | 135 +-
drivers/gpu/drm/msm/msm_drv.h | 81 +-
drivers/gpu/drm/msm/msm_kms.h | 8 +
64 files changed, 31989 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
The patch is too large for dri-devel, please refer to:
https://gitlab.freedesktop.org/seanpaul/dpu-staging/commit/00601828c2959f91397e938a9632741f42e994c5
--
Sean Paul, Software Engineer, Google / Chromium OS
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