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From: Sean Paul <seanpaul@chromium.org>
To: abhinavk@codeaurora.org, architt@codeaurora.org,
	chandanu@codeaurora.org, jsanka@codeaurora.org,
	jcrouse@codeaurora.org, ryadav@codeaurora.org,
	seanpaul@chromium.org, skolluku@codeaurora.org,
	dri-devel@lists.freedesktop.org, robdclark@gmail.com,
	airlied@linux.ie, freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org, nganji@codeaurora.org,
	hoegsberg@chromium.org, dovizu@chromium.org, robh+dt@kernel.org
Cc: Neil Armstrong <narmstrong@baylibre.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	Lloyd Atkinson <latkinso@codeaurora.org>,
	Sibi Sankar <sibis@codeaurora.org>,
	Daniel Mack <daniel@zonque.org>
Subject: [PATCH v3 04/19] drm/msm/dsi: adjust dsi timing for dual dsi mode
Date: Fri, 20 Jul 2018 16:42:55 -0400	[thread overview]
Message-ID: <20180720204315.19054-5-seanpaul@chromium.org> (raw)
In-Reply-To: <20180720204315.19054-1-seanpaul@chromium.org>

From: Chandan Uddaraju <chandanu@codeaurora.org>

For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.

Changes in v3:
- Added Archit's R-b
- Rebase on dsi cleanup set in msm-next

Cc: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/msm/dsi/dsi.h         | 10 +++--
 drivers/gpu/drm/msm/dsi/dsi_cfg.h     |  2 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c    | 65 ++++++++++++++++++++++-----
 drivers/gpu/drm/msm/dsi/dsi_manager.c |  7 +--
 4 files changed, 64 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index dfa049d876bd..d3f613c76ffa 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -163,7 +163,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host,
 int msm_dsi_host_enable(struct mipi_dsi_host *host);
 int msm_dsi_host_disable(struct mipi_dsi_host *host);
 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
-			struct msm_dsi_phy_shared_timings *phy_shared_timings);
+			struct msm_dsi_phy_shared_timings *phy_shared_timings,
+			bool is_dual_dsi);
 int msm_dsi_host_power_off(struct mipi_dsi_host *host);
 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
 					struct drm_display_mode *mode);
@@ -176,7 +177,8 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
 			struct msm_dsi_pll *src_pll);
 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
-	struct msm_dsi_phy_clk_request *clk_req);
+	struct msm_dsi_phy_clk_request *clk_req,
+	bool is_dual_dsi);
 void msm_dsi_host_destroy(struct mipi_dsi_host *host);
 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
 					struct drm_device *dev);
@@ -196,8 +198,8 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova);
 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
 int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);
 
 /* dsi phy */
 struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index a795a062b779..16c507911110 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -48,7 +48,7 @@ struct msm_dsi_host_cfg_ops {
 	void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
 	void (*tx_buf_put)(struct msm_dsi_host *msm_host);
 	int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t *iova);
-	int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
+	int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool is_dual_dsi);
 };
 
 struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index bb00e0f150cb..f6c6eddbcec7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -118,6 +118,7 @@ struct msm_dsi_host {
 	struct clk *byte_intf_clk;
 
 	u32 byte_clk_rate;
+	u32 pixel_clk_rate;
 	u32 esc_clk_rate;
 
 	/* DSI v2 specific clocks */
@@ -523,7 +524,7 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
 		goto error;
 	}
 
-	ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
 	if (ret) {
 		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
 		goto error;
@@ -604,7 +605,7 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
 		goto error;
 	}
 
-	ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
 	if (ret) {
 		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
 		goto error;
@@ -663,7 +664,7 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
 	clk_disable_unprepare(msm_host->byte_clk);
 }
 
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi)
 {
 	struct drm_display_mode *mode = msm_host->mode;
 	u8 lanes = msm_host->lanes;
@@ -671,6 +672,16 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
 	u32 pclk_rate;
 
 	pclk_rate = mode->clock * 1000;
+
+	/*
+	 * For dual DSI mode, the current DRM mode has the complete width of the
+	 * panel. Since, the complete panel is driven by two DSI controllers,
+	 * theclock rates have to be split between the two dsi controllers.
+	 * Adjust the byte and pixel clock rates for each dsi host accordingly.
+	 */
+	if (is_dual_dsi)
+		pclk_rate /= 2;
+
 	if (lanes > 0) {
 		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
 	} else {
@@ -685,7 +696,7 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
 	return 0;
 }
 
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
 {
 	struct drm_display_mode *mode = msm_host->mode;
 	u8 lanes = msm_host->lanes;
@@ -695,14 +706,26 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
 	unsigned long byte_mhz;
 
 	pclk_rate = mode->clock * 1000;
+
+	/*
+	 * For dual DSI mode, the current DRM mode has the complete width of the
+	 * panel. Since, the complete panel is driven by two DSI controllers,
+	 * theclock rates have to be split between the two dsi controllers.
+	 * Adjust the byte and pixel clock rates for each dsi host accordingly.
+	 */
+	if (is_dual_dsi)
+		pclk_rate /= 2;
+
 	if (lanes > 0) {
 		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
 	} else {
 		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
 		msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
 	}
+	msm_host->pixel_clk_rate = pclk_rate;
 
-	DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
+				msm_host->byte_clk_rate);
 
 	msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
 
@@ -897,7 +920,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
 	dsi_write(msm_host, REG_DSI_CTRL, data);
 }
 
-static void dsi_timing_setup(struct msm_dsi_host *msm_host)
+static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
 {
 	struct drm_display_mode *mode = msm_host->mode;
 	u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
@@ -909,10 +932,26 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host)
 	u32 ha_end = ha_start + mode->hdisplay;
 	u32 va_start = v_total - mode->vsync_start;
 	u32 va_end = va_start + mode->vdisplay;
+	u32 hdisplay = mode->hdisplay;
 	u32 wc;
 
 	DBG("");
 
+	/*
+	 * For dual DSI mode, the current DRM mode has
+	 * the complete width of the panel. Since, the complete
+	 * panel is driven by two DSI controllers, the horizontal
+	 * timings have to be split between the two dsi controllers.
+	 * Adjust the DSI host timing values accordingly.
+	 */
+	if (is_dual_dsi) {
+		h_total /= 2;
+		hs_end /= 2;
+		ha_start /= 2;
+		ha_end /= 2;
+		hdisplay /= 2;
+	}
+
 	if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
 		dsi_write(msm_host, REG_DSI_ACTIVE_H,
 			DSI_ACTIVE_H_START(ha_start) |
@@ -933,7 +972,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host)
 			DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
 	} else {		/* command mode */
 		/* image data and 1 byte write_memory_start cmd */
-		wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+		wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
 
 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
 			DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
@@ -943,7 +982,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host)
 					MIPI_DSI_DCS_LONG_WRITE));
 
 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
-			DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
+			DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) |
 			DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
 	}
 }
@@ -2217,13 +2256,14 @@ void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
 }
 
 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
-	struct msm_dsi_phy_clk_request *clk_req)
+			struct msm_dsi_phy_clk_request *clk_req,
+			bool is_dual_dsi)
 {
 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
 	int ret;
 
-	ret = cfg_hnd->ops->calc_clk_rate(msm_host);
+	ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi);
 	if (ret) {
 		pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
 		return;
@@ -2285,7 +2325,8 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
 }
 
 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
-			struct msm_dsi_phy_shared_timings *phy_shared_timings)
+			struct msm_dsi_phy_shared_timings *phy_shared_timings,
+			bool is_dual_dsi)
 {
 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
@@ -2321,7 +2362,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
 		goto fail_disable_clk;
 	}
 
-	dsi_timing_setup(msm_host);
+	dsi_timing_setup(msm_host, is_dual_dsi);
 	dsi_sw_reset(msm_host);
 	dsi_ctrl_config(msm_host, true, phy_shared_timings);
 
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 4cb1cb68878b..3bb506b44a4b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -134,8 +134,9 @@ static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
 {
 	struct msm_dsi_phy_clk_request clk_req;
 	int ret;
+	bool is_dual_dsi = IS_DUAL_DSI();
 
-	msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req);
+	msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);
 
 	ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);
 	msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
@@ -458,7 +459,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
 	if (is_dual_dsi && (DSI_1 == id))
 		return;
 
-	ret = msm_dsi_host_power_on(host, &phy_shared_timings[id]);
+	ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi);
 	if (ret) {
 		pr_err("%s: power on host %d failed, %d\n", __func__, id, ret);
 		goto host_on_fail;
@@ -466,7 +467,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
 
 	if (is_dual_dsi && msm_dsi1) {
 		ret = msm_dsi_host_power_on(msm_dsi1->host,
-					    &phy_shared_timings[DSI_1]);
+				&phy_shared_timings[DSI_1], is_dual_dsi);
 		if (ret) {
 			pr_err("%s: power on host1 failed, %d\n",
 							__func__, ret);
-- 
Sean Paul, Software Engineer, Google / Chromium OS

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  parent reply	other threads:[~2018-07-20 20:42 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-20 20:42 [PATCH v3 00/19] drm/msm: Add support for SDM845 Display Processing Unit (DPU) Sean Paul
     [not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-20 20:42   ` [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding Sean Paul
2018-07-20 20:42   ` [PATCH v3 02/19] drm: Add support for pps and compression mode command packet Sean Paul
2018-07-20 20:42   ` [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode Sean Paul
2018-07-20 20:42   ` [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly Sean Paul
2018-07-20 20:42   ` [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks Sean Paul
2018-07-20 20:43   ` [PATCH v3 10/19] drm/msm: enable zpos normalization Sean Paul
2018-07-20 20:43   ` [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Sean Paul
2018-07-20 20:43   ` [PATCH v3 13/19] drm/msm: #define MDP version numbers Sean Paul
2018-07-20 20:43   ` [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path Sean Paul
2018-07-20 20:43   ` [PATCH v3 15/19] drm/msm: #define MAX_<OBJECT> in msm_drv.h Sean Paul
2018-07-20 20:43   ` [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions Sean Paul
2018-07-20 20:43   ` [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms Sean Paul
2018-07-20 20:43   ` [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
2018-07-24 23:31     ` Rob Herring
2018-07-20 20:43   ` [PATCH v3 19/19] drm/msm: Add SDM845 DPU support Sean Paul
2018-07-20 20:42 ` [PATCH v3 03/19] drm: add msm compressed format modifiers Sean Paul
     [not found]   ` <20180720204315.19054-4-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-25 14:09     ` Stanimir Varbanov
2018-07-25 23:09       ` Jeykumar Sankaran
2018-07-26  9:37         ` Stanimir Varbanov
     [not found]         ` <d224e3ff142d687c07233f70864206af-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-07-26 11:45           ` Rob Clark
     [not found]             ` <CAF6AEGvrpmNVtYJxMR2Ka5S3_oeGm8C_SbeOPZR_TAONhS0_KA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-26 14:43               ` [PATCH v4 " Sean Paul
2018-07-20 20:42 ` Sean Paul [this message]
2018-07-20 20:42 ` [PATCH v3 06/19] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll Sean Paul
2018-07-20 20:43 ` [PATCH v3 09/19] drm/msm/mdp5: subclass msm_mdss for mdp5 Sean Paul
2018-07-20 20:43 ` [PATCH v3 12/19] drm/msm: Clean up dangling atomic_wq Sean Paul

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