From: Sean Paul <sean@poorly.run>
To: Abhinav Kumar <abhinavk@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, dianders@chromium.org,
dri-devel@lists.freedesktop.org, swboyd@chromium.org,
seanpaul@chromium.org, hoegsberg@google.com,
chandanu@codeaurora.org
Subject: Re: [PATCH] drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver
Date: Thu, 11 Oct 2018 11:15:31 -0400 [thread overview]
Message-ID: <20181011151531.GB154175@art_vandelay> (raw)
In-Reply-To: <1539223593-339-1-git-send-email-abhinavk@codeaurora.org>
On Wed, Oct 10, 2018 at 07:06:33PM -0700, Abhinav Kumar wrote:
> Fix the dsi clock names in the DSI 10nm PLL driver to
> match the names in the dispcc driver as those are
> according to the clock plan of the chipset.
You should also update the clock diagram names at the top of the file.
Sean
>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> index 41bec57..8304024 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> @@ -690,7 +690,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
>
> hws[num++] = hw;
>
> - snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
>
> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
> @@ -739,7 +739,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
>
> hws[num++] = hw;
>
> - snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id);
> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
> snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
>
> /* PIX CLK DIV : DIV_CTRL_7_4*/
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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prev parent reply other threads:[~2018-10-11 15:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-11 2:06 [PATCH] drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver Abhinav Kumar
2018-10-11 15:15 ` Sean Paul [this message]
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