From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH 2/2] iommu/arm-smmu: Add support for non-coherent page table mappings Date: Sun, 20 Jan 2019 00:01:18 +0000 Message-ID: <20190120000117.GH26876@brain-police> References: <20190117092718.1396-1-vivek.gautam@codeaurora.org> <20190117092718.1396-3-vivek.gautam@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20190117092718.1396-3-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Vivek Gautam Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org On Thu, Jan 17, 2019 at 02:57:18PM +0530, Vivek Gautam wrote: > Adding a device tree option for arm smmu to enable non-cacheable > memory for page tables. > We already enable a smmu feature for coherent walk based on > whether the smmu device is dma-coherent or not. Have an option > to enable non-cacheable page table memory to force set it for > particular smmu devices. Hmm, I must be missing something here. What is the difference between this new property, and simply omitting dma-coherent on the SMMU? Will