* [PATCH] clk: gcc-qcs404: Add PCIe resets
@ 2019-05-02 0:21 Bjorn Andersson
2019-05-02 0:21 ` Bjorn Andersson
2019-05-02 10:53 ` Marc Gonzalez
0 siblings, 2 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-05-02 0:21 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-clk, linux-kernel,
devicetree
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v2:
- Rebased patch
drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a54807eb3b28..29cf464dd2c8 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2766,6 +2766,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
+ [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
+ [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
+ [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
+ [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
[GCC_EMAC_BCR] = { 0x4e000 },
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 454b3f43f538..5959399fed2e 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -166,5 +166,12 @@
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#define GCC_CDSP_RESTART 14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
+#define GCC_PCIE_0_AHB_ARES 15
+#define GCC_PCIE_0_AXI_SLAVE_ARES 16
+#define GCC_PCIE_0_AXI_MASTER_ARES 17
+#define GCC_PCIE_0_CORE_STICKY_ARES 18
+#define GCC_PCIE_0_SLEEP_ARES 19
+#define GCC_PCIE_0_PIPE_ARES 20
#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] clk: gcc-qcs404: Add PCIe resets
2019-05-02 0:21 [PATCH] clk: gcc-qcs404: Add PCIe resets Bjorn Andersson
@ 2019-05-02 0:21 ` Bjorn Andersson
2019-05-02 10:53 ` Marc Gonzalez
1 sibling, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-05-02 0:21 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-clk, linux-kernel,
devicetree
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v2:
- Rebased patch
drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a54807eb3b28..29cf464dd2c8 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2766,6 +2766,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
+ [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
+ [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
+ [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
+ [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
[GCC_EMAC_BCR] = { 0x4e000 },
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 454b3f43f538..5959399fed2e 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -166,5 +166,12 @@
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
#define GCC_CDSP_RESTART 14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
+#define GCC_PCIE_0_AHB_ARES 15
+#define GCC_PCIE_0_AXI_SLAVE_ARES 16
+#define GCC_PCIE_0_AXI_MASTER_ARES 17
+#define GCC_PCIE_0_CORE_STICKY_ARES 18
+#define GCC_PCIE_0_SLEEP_ARES 19
+#define GCC_PCIE_0_PIPE_ARES 20
#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: gcc-qcs404: Add PCIe resets
2019-05-02 0:21 [PATCH] clk: gcc-qcs404: Add PCIe resets Bjorn Andersson
2019-05-02 0:21 ` Bjorn Andersson
@ 2019-05-02 10:53 ` Marc Gonzalez
2019-05-02 11:20 ` Niklas Cassel
1 sibling, 1 reply; 6+ messages in thread
From: Marc Gonzalez @ 2019-05-02 10:53 UTC (permalink / raw)
To: Bjorn Andersson, Niklas Cassel; +Cc: Stephen Boyd, Rob Herring, MSM, linux-clk
On 02/05/2019 02:21, Bjorn Andersson wrote:
> diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> index 454b3f43f538..5959399fed2e 100644
> --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> @@ -166,5 +166,12 @@
> #define GCC_PCIEPHY_0_PHY_BCR 12
> #define GCC_EMAC_BCR 13
> #define GCC_CDSP_RESTART 14
> +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
Seems weird that there would be two names for the same entry at index 14?
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: gcc-qcs404: Add PCIe resets
2019-05-02 10:53 ` Marc Gonzalez
@ 2019-05-02 11:20 ` Niklas Cassel
2019-05-02 20:43 ` Stephen Boyd
0 siblings, 1 reply; 6+ messages in thread
From: Niklas Cassel @ 2019-05-02 11:20 UTC (permalink / raw)
To: Marc Gonzalez; +Cc: Bjorn Andersson, Stephen Boyd, Rob Herring, MSM, linux-clk
On Thu, May 02, 2019 at 12:53:33PM +0200, Marc Gonzalez wrote:
> On 02/05/2019 02:21, Bjorn Andersson wrote:
>
> > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > index 454b3f43f538..5959399fed2e 100644
> > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > @@ -166,5 +166,12 @@
> > #define GCC_PCIEPHY_0_PHY_BCR 12
> > #define GCC_EMAC_BCR 13
> > #define GCC_CDSP_RESTART 14
> > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
>
> Seems weird that there would be two names for the same entry at index 14?
Changes since v2:
- Rebased patch
The proper tag in the subject should have been [PATCH v2].
This is most likely an issue caused by the rebase.
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: gcc-qcs404: Add PCIe resets
2019-05-02 11:20 ` Niklas Cassel
@ 2019-05-02 20:43 ` Stephen Boyd
2019-05-02 21:53 ` Bjorn Andersson
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Boyd @ 2019-05-02 20:43 UTC (permalink / raw)
To: Marc Gonzalez, Niklas Cassel; +Cc: Bjorn Andersson, Rob Herring, MSM, linux-clk
Quoting Niklas Cassel (2019-05-02 04:20:24)
> On Thu, May 02, 2019 at 12:53:33PM +0200, Marc Gonzalez wrote:
> > On 02/05/2019 02:21, Bjorn Andersson wrote:
> >
> > > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > > index 454b3f43f538..5959399fed2e 100644
> > > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > > @@ -166,5 +166,12 @@
> > > #define GCC_PCIEPHY_0_PHY_BCR 12
> > > #define GCC_EMAC_BCR 13
> > > #define GCC_CDSP_RESTART 14
> > > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
> >
> > Seems weird that there would be two names for the same entry at index 14?
>
> Changes since v2:
> - Rebased patch
>
> The proper tag in the subject should have been [PATCH v2].
>
> This is most likely an issue caused by the rebase.
>
Please resend then.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: gcc-qcs404: Add PCIe resets
2019-05-02 20:43 ` Stephen Boyd
@ 2019-05-02 21:53 ` Bjorn Andersson
0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-05-02 21:53 UTC (permalink / raw)
To: Stephen Boyd; +Cc: Marc Gonzalez, Niklas Cassel, Rob Herring, MSM, linux-clk
On Thu 02 May 13:43 PDT 2019, Stephen Boyd wrote:
> Quoting Niklas Cassel (2019-05-02 04:20:24)
> > On Thu, May 02, 2019 at 12:53:33PM +0200, Marc Gonzalez wrote:
> > > On 02/05/2019 02:21, Bjorn Andersson wrote:
> > >
> > > > diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > > > index 454b3f43f538..5959399fed2e 100644
> > > > --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > > > +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> > > > @@ -166,5 +166,12 @@
> > > > #define GCC_PCIEPHY_0_PHY_BCR 12
> > > > #define GCC_EMAC_BCR 13
> > > > #define GCC_CDSP_RESTART 14
> > > > +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
> > >
> > > Seems weird that there would be two names for the same entry at index 14?
> >
> > Changes since v2:
> > - Rebased patch
> >
> > The proper tag in the subject should have been [PATCH v2].
> >
> > This is most likely an issue caused by the rebase.
> >
>
> Please resend then.
>
Yeah, I screwed up the rebase. v4 is coming.
Thanks Marc,
Bjorn
^ permalink raw reply [flat|nested] 6+ messages in thread
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2019-05-02 0:21 [PATCH] clk: gcc-qcs404: Add PCIe resets Bjorn Andersson
2019-05-02 0:21 ` Bjorn Andersson
2019-05-02 10:53 ` Marc Gonzalez
2019-05-02 11:20 ` Niklas Cassel
2019-05-02 20:43 ` Stephen Boyd
2019-05-02 21:53 ` Bjorn Andersson
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