From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFB2EC28CC5 for ; Wed, 5 Jun 2019 12:19:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9469B206BA for ; Wed, 5 Jun 2019 12:19:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727408AbfFEMTF (ORCPT ); Wed, 5 Jun 2019 08:19:05 -0400 Received: from foss.arm.com ([217.140.101.70]:58854 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727172AbfFEMTF (ORCPT ); Wed, 5 Jun 2019 08:19:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 993C180D; Wed, 5 Jun 2019 05:19:04 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC1EB3F246; Wed, 5 Jun 2019 05:19:02 -0700 (PDT) Date: Wed, 5 Jun 2019 13:19:00 +0100 From: Will Deacon To: Marc Gonzalez , joro@8bytes.org Cc: Robin Murphy , MSM , Linux ARM , iommu , AngeloGioacchino Del Regno , Jeffrey Hugo , Andy Gross , Bjorn Andersson Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> References: <20190529130559.GB11023@fuggles.cambridge.arm.com> <84791515-e0ae-0322-78aa-02ca0b40d157@free.fr> <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org [+Joerg on To:] On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote: > From: Robin Murphy > > Apparently, some Qualcomm arm64 platforms which appear to expose their > SMMU global register space are still, in fact, using a hypervisor to > mediate it by trapping and emulating register accesses. Sadly, some > deployed versions of said trapping code have bugs wherein they go > horribly wrong for stores using r31 (i.e. XZR/WZR) as the source > register. > > While this can be mitigated for GCC today by tweaking the constraints > for the implementation of writel_relaxed(), to avoid any potential > arms race with future compilers more aggressively optimising register > allocation, the simple way is to just remove all the problematic > constant zeros. For the write-only TLB operations, the actual value is > irrelevant anyway and any old nearby variable will provide a suitable > GPR to encode. The one point at which we really do need a zero to clear > a context bank happens before any of the TLB maintenance where crashes > have been reported, so is apparently not a problem... :/ > > Reported-by: AngeloGioacchino Del Regno > Tested-by: Marc Gonzalez > Signed-off-by: Robin Murphy > Signed-off-by: Marc Gonzalez Acked-by: Will Deacon Joerg -- Please can you take this as a fix for 5.2, with a Cc stable? Cheers, Will