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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 124sm430653pfd.63.2019.06.07.20.26.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Jun 2019 20:26:16 -0700 (PDT) Date: Fri, 7 Jun 2019 20:26:13 -0700 From: Bjorn Andersson To: Sricharan R Cc: robh+dt@kernel.org, sboyd@codeaurora.org, linus.walleij@linaro.org, agross@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver Message-ID: <20190608032613.GC24059@builder> References: <1559754961-26783-1-git-send-email-sricharan@codeaurora.org> <1559754961-26783-2-git-send-email-sricharan@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1559754961-26783-2-git-send-email-sricharan@codeaurora.org> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote: > Add initial pinctrl driver to support pin configuration with > pinctrl framework for ipq6018. > > Signed-off-by: Sricharan R > Signed-off-by: Rajkumar Ayyasamy > Signed-off-by: speriaka These should start with the author, then followed by each person that handled the patch on its way to the list - so your name should probably be last. If you have more than one author add Co-developed-by, in addition to the Signed-off-by. And please spell our speriaka's first and last name. [..] > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt [..] > +- #gpio-cells: > + Usage: required > + Value type: > + Definition: must be 2. Specifying the pin number and flags, as defined > + in You're missing the required "gpio-ranges" property. > + [..] > +- function: > + Usage: required > + Value type: > + Definition: Specify the alternative function to be configured for the > + specified pins. Functions are only valid for gpio pins. > + Valid values are: > + adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, Please indent these. [..] The rest should be in a separate patch from the binding. > diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig [..] > +enum ipq6018_functions { [..] > + msm_mux_NA, I like when these are sorted, and if you make the last entry msm_mux__ the msm_pingroup array becomes easier to read. > +}; [..] > +static const struct msm_function ipq6018_functions[] = { [..] > + FUNCTION(gcc_tlmm), As above, please sort these. > +}; > + > +static const struct msm_pingroup ipq6018_groups[] = { > + PINGROUP(0, qpic_pad, wci20, qdss_traceclk_b, NA, burn0, NA, NA, NA, > + NA), Please ignore the 80-char and skip the line breaks. > + PINGROUP(1, qpic_pad, mac12, qdss_tracectl_b, NA, burn1, NA, NA, NA, > + NA), > + PINGROUP(2, qpic_pad, wci20, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), > + PINGROUP(3, qpic_pad, mac01, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), > + PINGROUP(4, qpic_pad, mac01, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), > + PINGROUP(5, qpic_pad4, mac21, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), Is there a reason to keep qpic_padN as separate functions from qpic_pad? [..] > +static struct platform_driver ipq6018_pinctrl_driver = { > + .driver = { > + .name = "ipq6018-pinctrl", > + .owner = THIS_MODULE, .owner is populated automagically by platform_driver_register, so please omit this. > + .of_match_table = ipq6018_pinctrl_of_match, > + }, > + .probe = ipq6018_pinctrl_probe, > + .remove = msm_pinctrl_remove, > +}; Regards, Bjorn