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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id q198sm252178pfq.155.2019.06.12.11.28.53 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 12 Jun 2019 11:28:54 -0700 (PDT) Date: Wed, 12 Jun 2019 11:28:52 -0700 From: Bjorn Andersson To: Jeffrey Hugo Cc: Joerg Roedel , Will Deacon , Robin Murphy , Patrick Daly , Jeffrey Hugo , MSM , lkml , iommu@lists.linux-foundation.org, Vivek Gautam , linux-arm-kernel@lists.infradead.org Subject: Re: [RFC 2/2] iommu: arm-smmu: Don't blindly use first SMR to calculate mask Message-ID: <20190612182852.GA4814@minitux> References: <20190605210856.20677-1-bjorn.andersson@linaro.org> <20190605210856.20677-3-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.12.0 (2019-05-25) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 12 Jun 10:58 PDT 2019, Jeffrey Hugo wrote: > On Wed, Jun 5, 2019 at 3:09 PM Bjorn Andersson > wrote: > > > > With the SMRs inherited from the bootloader the first SMR might actually > > be valid and in use. As such probing the SMR mask using the first SMR > > might break a stream in use. Search for an unused stream and use this to > > probe the SMR mask. > > > > Signed-off-by: Bjorn Andersson > > Reviewed-by: Jeffrey Hugo > > I don't quite like the situation where the is no SMR to compute the mask, but I > think the way you've handled it is the best option/ > Right, if this happens we would end up using the smr_mask that was previously calculated. We just won't update it based on the hardware. > I'm curious, why is this not included in patch #1? Seems like patch > #1 introduces > the issue, yet doesn't also fix it. > You're right, didn't think about that. This needs to either predate that patch or be included in it. Thanks, Bjorn > > --- > > drivers/iommu/arm-smmu.c | 20 ++++++++++++++++---- > > 1 file changed, 16 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > index c8629a656b42..0c6f5fe6f382 100644 > > --- a/drivers/iommu/arm-smmu.c > > +++ b/drivers/iommu/arm-smmu.c > > @@ -1084,23 +1084,35 @@ static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) > > { > > void __iomem *gr0_base = ARM_SMMU_GR0(smmu); > > u32 smr; > > + int idx; > > > > if (!smmu->smrs) > > return; > > > > + for (idx = 0; idx < smmu->num_mapping_groups; idx++) { > > + smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx)); > > + if (!(smr & SMR_VALID)) > > + break; > > + } > > + > > + if (idx == smmu->num_mapping_groups) { > > + dev_err(smmu->dev, "Unable to compute streamid_mask\n"); > > + return; > > + } > > + > > /* > > * SMR.ID bits may not be preserved if the corresponding MASK > > * bits are set, so check each one separately. We can reject > > * masters later if they try to claim IDs outside these masks. > > */ > > smr = smmu->streamid_mask << SMR_ID_SHIFT; > > - writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); > > - smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); > > + writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(idx)); > > + smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx)); > > smmu->streamid_mask = smr >> SMR_ID_SHIFT; > > > > smr = smmu->streamid_mask << SMR_MASK_SHIFT; > > - writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); > > - smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); > > + writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(idx)); > > + smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(idx)); > > smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT; > > } > > > > -- > > 2.18.0 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel