From: kholk11@gmail.com
To: linux-arm-msm@vger.kernel.org
Cc: iommu@lists.linux-foundation.org, marijns95@gmail.com,
agross@kernel.org, robdclark@gmail.com, joro@8bytes.org,
AngeloGioacchino Del Regno <kholk11@gmail.com>
Subject: [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior
Date: Thu, 26 Sep 2019 14:05:12 +0200 [thread overview]
Message-ID: <20190926120516.4981-3-kholk11@gmail.com> (raw)
In-Reply-To: <20190926120516.4981-1-kholk11@gmail.com>
From: AngeloGioacchino Del Regno <kholk11@gmail.com>
As also stated in the arm-smmu driver, we must write the TCR before
writing the TTBRs, since the TCR determines the access behavior of
some fields.
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
drivers/iommu/qcom_iommu.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 5837556af147..8431fb97a50f 100644
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -245,6 +245,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
ctx->secure_init = true;
}
+ /* TCR */
+ iommu_writel(ctx, ARM_SMMU_CB_TCR2,
+ (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
+ FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
+ iommu_writel(ctx, ARM_SMMU_CB_TCR,
+ pgtbl_cfg.arm_lpae_s1_cfg.tcr);
+
/* TTBRs */
iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
@@ -253,13 +260,6 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
FIELD_PREP(TTBRn_ASID, ctx->asid));
- /* TCR */
- iommu_writel(ctx, ARM_SMMU_CB_TCR2,
- (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
- FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
- iommu_writel(ctx, ARM_SMMU_CB_TCR,
- pgtbl_cfg.arm_lpae_s1_cfg.tcr);
-
/* MAIRs (stage-1 only) */
iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
--
2.21.0
next prev parent reply other threads:[~2019-09-26 12:05 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 12:05 [PATCH 0/6] Add support for QCOM IOMMU v2 and 500 kholk11
2019-09-26 12:05 ` [PATCH 1/6] iommu/qcom: Use the asid read from device-tree if specified kholk11
2019-09-26 20:06 ` Rob Clark
2019-09-26 12:05 ` kholk11 [this message]
2019-09-26 12:05 ` [PATCH 3/6] iommu/qcom: Properly reset the IOMMU context kholk11
2019-09-26 12:05 ` [PATCH 4/6] iommu/qcom: Add support for AArch64 IOMMU pagetables kholk11
2019-09-26 12:05 ` [PATCH 5/6] iommu/qcom: Index contexts by asid number to allow asid 0 kholk11
2019-09-26 12:05 ` [PATCH 6/6] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts kholk11
-- strict thread matches above, loose matches on Subject: below --
2022-05-27 21:28 [PATCH 0/6] Fix and extend Qualcomm IOMMU support Konrad Dybcio
2022-05-27 21:28 ` [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior Konrad Dybcio
2022-05-31 15:55 ` Will Deacon
2022-05-31 16:26 ` Robin Murphy
2022-06-05 22:06 ` Marijn Suijten
2022-06-08 10:27 ` AngeloGioacchino Del Regno
2022-06-08 10:54 ` Robin Murphy
2022-06-08 11:03 ` AngeloGioacchino Del Regno
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