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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id s18sm22092805pfm.27.2019.11.28.14.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2019 14:11:27 -0800 (PST) Date: Thu, 28 Nov 2019 14:11:24 -0800 From: Bjorn Andersson To: Matthias Kaehlcke Cc: Sandeep Maheswaram , Andy Gross , Rob Herring , Mark Rutland , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam Subject: Re: [PATCH v3 1/1] arm64: dts: qcom: sc7180: Add USB related nodes Message-ID: <20191128221124.GM82109@yoga> References: <1573795421-13989-1-git-send-email-sanm@codeaurora.org> <1573795421-13989-2-git-send-email-sanm@codeaurora.org> <20191122005117.GM27773@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122005117.GM27773@google.com> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu 21 Nov 16:51 PST 2019, Matthias Kaehlcke wrote: > Hi Sandeep, > > On Fri, Nov 15, 2019 at 10:53:41AM +0530, Sandeep Maheswaram wrote: > > Add nodes for DWC3 USB controller, QMP and QUSB PHYs. > > > > Signed-off-by: Sandeep Maheswaram > > Reviewed-by: Stephen Boyd > > --- > > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 25 ++++++++ > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 105 ++++++++++++++++++++++++++++++++ > > 2 files changed, 130 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > index 666e9b9..2c7dbdc 100644 > > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > > > ... > > > > + usb_1: usb@a6f8800 { > > + compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; > > + reg = <0 0x0a6f8800 0 0x400>; > > + status = "disabled"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + dma-ranges; > > + > > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > > + "sleep"; > > + > > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > > + assigned-clock-rates = <19200000>, <150000000>; > > + > > + interrupts = , > > + , > > + , > > + ; > > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > > + > > + power-domains = <&gcc USB30_PRIM_GDSC>; > > + > > + resets = <&gcc GCC_USB30_PRIM_BCR>; > > + > > + usb_1_dwc3: dwc3@a600000 { > > + compatible = "snps,dwc3"; > > + reg = <0 0x0a600000 0 0xe000>; > > + interrupts = ; > > + iommus = <&apps_smmu 0x540 0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_enblslpm_quirk; > > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + }; > > I see the following message at boot: > > [ 4.248436] dwc3 a600000.dwc3: Failed to get clk 'ref': -2 > dwc3-qcom picks up the clocks per the names of the binding, but then dwc3 tries to pick up the same clocks based on the generic names. At some point it would be nice to figure out how to have these two play nice with each other, but for now it's a "harmless" error print - which has consumed many hours of unnecessary debugging by various people... Regards, Bjorn