Re: [PATCH v2 3/5] phy: qcom-qmp: Add optional SW reset

[Vinod Koul <vkoul@kernel.org>]

Hi Manu,

On 23-12-19, 14:38, Manu Gautam wrote:
> 
> On 12/20/2019 3:47 PM, Vinod Koul wrote:
> > For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
> > then deassert it, so add optional has_sw_reset flag and use that to
> > configure the QPHY_SW_RESET register.
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > index 1196c85aa023..47a66d55107d 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > @@ -168,6 +168,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
> >  static const unsigned int sm8150_ufsphy_regs_layout[] = {
> >  	[QPHY_START_CTRL]		= QPHY_V4_PHY_START,
> >  	[QPHY_PCS_READY_STATUS]		= QPHY_V4_PCS_READY_STATUS,
> > +	[QPHY_SW_RESET]			= QPHY_V4_SW_RESET,
> >  };
> >  
> >  static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
> > @@ -1023,6 +1024,9 @@ struct qmp_phy_cfg {
> >  
> >  	/* true, if PCS block has no separate SW_RESET register */
> >  	bool no_pcs_sw_reset;
> > +
> > +	/* true if sw reset needs to be invoked */
> > +	bool has_sw_reset;
> 
> 
> There is no need to add new flag. Existing code will take care of it for UFS once you
> clear no_pcs_sw_reset flag.
> 
> >  };
> >  
> >  /**
> > @@ -1391,6 +1395,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> >  
> >  	.is_dual_lane_phy	= true,
> >  	.no_pcs_sw_reset	= true,
> > +	.has_sw_reset		= true,
> >  };
> >  
> >  static void qcom_qmp_phy_configure(void __iomem *base,
> > @@ -1475,6 +1480,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> >  			     SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> >  	}
> >  
> > +	if (cfg->has_sw_reset)
> > +		qphy_setbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> > +
> 
> Not needed. POR value of the bit is '1'.
> 
> 
> >  	if (cfg->has_phy_com_ctrl)
> >  		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> >  			     SW_PWRDN);
> > @@ -1651,6 +1659,9 @@ static int qcom_qmp_phy_enable(struct phy *phy)
> >  	if (cfg->has_phy_dp_com_ctrl)
> >  		qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
> >  
> > +	if (cfg->has_sw_reset)
> > +		qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> > +
> 
> There is no need to add UFS specific change here as existing PHY driver can
> handle PCS based PHY sw_reset and already does it for USB and PCIe.

Thanks for the explanation in this and previous version.

I confirm that adding sw_reset and clearing .no_pcs_sw_reset does make
it work for me on UFS on SM8150.

I will drop this patch and send the update in v3

-- 
~Vinod