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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m101sm557380pje.13.2020.02.03.15.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 15:31:42 -0800 (PST) Date: Mon, 3 Feb 2020 15:31:40 -0800 From: Bjorn Andersson To: Douglas Anderson Cc: Andrzej Hajda , Neil Armstrong , robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, Jeffrey Hugo , Daniel Vetter , Rob Clark , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart Subject: Re: [PATCH v3 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Message-ID: <20200203233140.GA311651@builder> References: <20191218223530.253106-1-dianders@chromium.org> <20191218143416.v3.1.Icb765d5799e9651e5249c0c27627ba33a9e411cf@changeid> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191218143416.v3.1.Icb765d5799e9651e5249c0c27627ba33a9e411cf@changeid> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote: > These two things were in one function. Split into two. This looks > like it's duplicating some code, but don't worry. This is is just in > preparation for future changes. > > This is intended to have zero functional change and will just make > future patches easier to understand. > > Signed-off-by: Douglas Anderson > Tested-by: Rob Clark > Reviewed-by: Rob Clark Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > > Changes in v3: None > Changes in v2: None > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 33 +++++++++++++++++++-------- > 1 file changed, 23 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index 43abf01ebd4c..2fb9370a76e6 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -417,6 +417,24 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata) > REFCLK_FREQ(i)); > } > > +static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata) > +{ > + unsigned int bit_rate_mhz, clk_freq_mhz; > + unsigned int val; > + struct drm_display_mode *mode = > + &pdata->bridge.encoder->crtc->state->adjusted_mode; > + > + /* set DSIA clk frequency */ > + bit_rate_mhz = (mode->clock / 1000) * > + mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); > + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); > + > + /* for each increment in val, frequency increases by 5MHz */ > + val = (MIN_DSI_CLK_FREQ_MHZ / 5) + > + (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); > + regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); > +} > + > /** > * LUT index corresponds to register value and > * LUT values corresponds to dp data rate supported > @@ -426,22 +444,16 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { > 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 > }; > > -static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata) > +static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) > { > - unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz; > - unsigned int val, i; > + unsigned int bit_rate_mhz, dp_rate_mhz; > + unsigned int i; > struct drm_display_mode *mode = > &pdata->bridge.encoder->crtc->state->adjusted_mode; > > /* set DSIA clk frequency */ > bit_rate_mhz = (mode->clock / 1000) * > mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); > - clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); > - > - /* for each increment in val, frequency increases by 5MHz */ > - val = (MIN_DSI_CLK_FREQ_MHZ / 5) + > - (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); > - regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); > > /* set DP data rate */ > dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) / > @@ -510,7 +522,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) > val); > > /* set dsi/dp clk frequency value */ > - ti_sn_bridge_set_dsi_dp_rate(pdata); > + ti_sn_bridge_set_dsi_rate(pdata); > + ti_sn_bridge_set_dp_rate(pdata); > > /* enable DP PLL */ > regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); > -- > 2.24.1.735.g03f4e72817-goog >