From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40D32C3F2D1 for ; Mon, 2 Mar 2020 16:43:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1289B2173E for ; Mon, 2 Mar 2020 16:43:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="XyzYOSEh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727359AbgCBQnk (ORCPT ); Mon, 2 Mar 2020 11:43:40 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:60619 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726997AbgCBQnk (ORCPT ); Mon, 2 Mar 2020 11:43:40 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1583167419; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=TbW7v6ETMwAyeMysipwO8G4evsiI1GMTYBqpmkfIiUg=; b=XyzYOSEhUPWsj5ErjcmVU+/ws05T5pysZiOANDbEWglrB0sL8UGBvOeSOyEt1TbUTXNdkyWy 8eOmmh269GYHaXQ8UCuW1RSRnjldqysewa1U1UAEvtDDRa32CuwROMQ/axCxhT0Os0nDVQF8 7zmeIIH3i96BCt8jNXdK87A9VbQ= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e5d37af.7f59f540a180-smtp-out-n02; Mon, 02 Mar 2020 16:43:27 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 773ABC4479C; Mon, 2 Mar 2020 16:43:27 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6A1AAC43383; Mon, 2 Mar 2020 16:43:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6A1AAC43383 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 2 Mar 2020 09:43:24 -0700 From: Jordan Crouse To: Sharat Masetty Cc: freedreno@lists.freedesktop.org, dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm: msm: a6x: Disable interrupts before recovery Message-ID: <20200302164324.GA708@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Sharat Masetty , freedreno@lists.freedesktop.org, dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <1583138836-20807-1-git-send-email-smasetty@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1583138836-20807-1-git-send-email-smasetty@codeaurora.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Mar 02, 2020 at 02:17:16PM +0530, Sharat Masetty wrote: > This patch disables interrupts in the GPU RBBM hang detect fault handler > before going to recovery. Okay, but why? What were you seeing? A little bit of extra description would make it easier to understand this change in the future. > > Signed-off-by: Sharat Masetty > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index dc8ec2c..4dd0f62 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -676,6 +676,9 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) > gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI), > gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); > > + /* Disable interrupts before going for a recovery*/ > + gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 0); > + And this is turning off all the interrupts, but the commit log only mentions the hang detect. In my experience, the hang detect usually only fires once until after reset, but if there are other interrupts that are bothering you then it makes sense to disable them but, again, this is good information for the commit log and or a code comment. Jordan > /* Turn off the hangcheck timer to keep it from bothering us */ > del_timer(&gpu->hangcheck_timer); > > -- > 1.9.1 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project