From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71F21C433DF for ; Wed, 24 Jun 2020 17:09:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C73B20823 for ; Wed, 24 Jun 2020 17:09:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="gF21QlSi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405231AbgFXRJg (ORCPT ); Wed, 24 Jun 2020 13:09:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405168AbgFXRJf (ORCPT ); Wed, 24 Jun 2020 13:09:35 -0400 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 686ACC061796 for ; Wed, 24 Jun 2020 10:09:35 -0700 (PDT) Received: by mail-pg1-x543.google.com with SMTP id f3so1716214pgr.2 for ; Wed, 24 Jun 2020 10:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=9MySW4mbbBRod9QicumBO9ww7psBdNIV6ZgeYYG3ji8=; b=gF21QlSigEqiKv7/jVfmhqua9KO64A4aVbVCZVSLvBaDQxKJevZAxFOLUwNNYPO678 oayFnL1yrtvZgJRSW+vlUylUtSudu9ugCMeZBvkv9I9z7EExjeqvz6p4jELGHqNp2bxM vGhMKmBo4E1ScaprADwWQWgpWVjbFKRrdMXUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=9MySW4mbbBRod9QicumBO9ww7psBdNIV6ZgeYYG3ji8=; b=uC0/+FQhiQAjfPoW9Y1diNpyweRJUL4Zo94pwrwKZBIGTj3OHpTpHHWdo1PnvaHwsg XJa6kONJwp3j1vfkEXUAgMAEOb7oNkzUwYk0ndHwmpAvhpJGsN1mq6CgefeB04jzQq6z 22c8cwEGHxu6X4HXZXCOY8m+mn4MsQKcr7zVPn3xxm7P5ikWY2zTmBK6oi8nEzyxjb0H tFZpuZD2gZkVDPB2NJZioaw2TXDQ4XiWYO9rTtgK0xUHn2jsv1/yAVWd2ft0bZ+3loDJ gt9FAH9ya6MM717bI0LgMS3J/z36HGXxrT26lrFCW6FFmQE0l+CK89Ncsx/bXGFXuhFs arZg== X-Gm-Message-State: AOAM53397BidMRQeLkrIfCFK2lw1c+avaILj/tzQQS/JeHobH3oWlJ8x UrdDNV9qfCfjoaIPHMHfAQOoCw== X-Google-Smtp-Source: ABdhPJycIWyjj9ea8bDVyXiRPwvu/3OunzszllngvVvuQDju1IWGrE2OaTYnFqWhsLFiJtbA+QzeZQ== X-Received: by 2002:a62:a110:: with SMTP id b16mr23448214pff.102.1593018574868; Wed, 24 Jun 2020 10:09:34 -0700 (PDT) Received: from localhost ([2620:15c:202:1:4fff:7a6b:a335:8fde]) by smtp.gmail.com with ESMTPSA id k7sm10422125pgh.46.2020.06.24.10.09.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Jun 2020 10:09:34 -0700 (PDT) Date: Wed, 24 Jun 2020 10:09:33 -0700 From: Matthias Kaehlcke To: Mark Brown Cc: Rajendra Nayak , bjorn.andersson@linaro.org, agross@kernel.org, robdclark@gmail.com, robdclark@chromium.org, stanimir.varbanov@linaro.org, viresh.kumar@linaro.org, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Alok Chauhan , Akash Asthana , linux-spi@vger.kernel.org Subject: Re: [PATCH v6 6/6] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Message-ID: <20200624170933.GB39073@google.com> References: <1592222564-13556-1-git-send-email-rnayak@codeaurora.org> <1592222564-13556-7-git-send-email-rnayak@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1592222564-13556-7-git-send-email-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Mark, do you plan to land this in your tree? I know you hate contentless pings, but since you acked this patch and usually don't seem to do that when patches go through your tree I want to make sure we aren't in a situation where everybody thinks that the patch will go through someone else's tree. Thanks Matthias On Mon, Jun 15, 2020 at 05:32:44PM +0530, Rajendra Nayak wrote: > QSPI needs to vote on a performance state of a power domain depending on > the clock rate. Add support for it by specifying the perf state/clock rate > as an OPP table in device tree. > > Signed-off-by: Rajendra Nayak > Reviewed-by: Matthias Kaehlcke > Acked-by: Mark Brown > Cc: Alok Chauhan > Cc: Akash Asthana > Cc: linux-spi@vger.kernel.org > --- > No functional change in v6, rebased over 5.8-rc1 > > drivers/spi/spi-qcom-qspi.c | 28 +++++++++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c > index 3c4f83b..ef51982 100644 > --- a/drivers/spi/spi-qcom-qspi.c > +++ b/drivers/spi/spi-qcom-qspi.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -139,6 +140,8 @@ struct qcom_qspi { > struct device *dev; > struct clk_bulk_data *clks; > struct qspi_xfer xfer; > + struct opp_table *opp_table; > + bool has_opp_table; > /* Lock to protect xfer and IRQ accessed registers */ > spinlock_t lock; > }; > @@ -235,7 +238,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master, > speed_hz = xfer->speed_hz; > > /* In regular operation (SBL_EN=1) core must be 4x transfer clock */ > - ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4); > + ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4); > if (ret) { > dev_err(ctrl->dev, "Failed to set core clk %d\n", ret); > return ret; > @@ -481,6 +484,20 @@ static int qcom_qspi_probe(struct platform_device *pdev) > master->handle_err = qcom_qspi_handle_err; > master->auto_runtime_pm = true; > > + ctrl->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); > + if (IS_ERR(ctrl->opp_table)) { > + ret = PTR_ERR(ctrl->opp_table); > + goto exit_probe_master_put; > + } > + /* OPP table is optional */ > + ret = dev_pm_opp_of_add_table(&pdev->dev); > + if (!ret) { > + ctrl->has_opp_table = true; > + } else if (ret != -ENODEV) { > + dev_err(&pdev->dev, "invalid OPP table in device tree\n"); > + goto exit_probe_master_put; > + } > + > pm_runtime_enable(dev); > > ret = spi_register_master(master); > @@ -488,6 +505,9 @@ static int qcom_qspi_probe(struct platform_device *pdev) > return 0; > > pm_runtime_disable(dev); > + if (ctrl->has_opp_table) > + dev_pm_opp_of_remove_table(&pdev->dev); > + dev_pm_opp_put_clkname(ctrl->opp_table); > > exit_probe_master_put: > spi_master_put(master); > @@ -498,11 +518,15 @@ static int qcom_qspi_probe(struct platform_device *pdev) > static int qcom_qspi_remove(struct platform_device *pdev) > { > struct spi_master *master = platform_get_drvdata(pdev); > + struct qcom_qspi *ctrl = spi_master_get_devdata(master); > > /* Unregister _before_ disabling pm_runtime() so we stop transfers */ > spi_unregister_master(master); > > pm_runtime_disable(&pdev->dev); > + if (ctrl->has_opp_table) > + dev_pm_opp_of_remove_table(&pdev->dev); > + dev_pm_opp_put_clkname(ctrl->opp_table); > > return 0; > } > @@ -512,6 +536,8 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) > struct spi_master *master = dev_get_drvdata(dev); > struct qcom_qspi *ctrl = spi_master_get_devdata(master); > > + /* Drop the performance state vote */ > + dev_pm_opp_set_rate(dev, 0); > clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks); > > return 0; > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >