From: Jordan Crouse <jcrouse@codeaurora.org>
To: kholk11@gmail.com
Cc: robdclark@gmail.com, sean@poorly.run, airlied@linux.ie,
daniel@ffwll.ch, konradybcio@gmail.com, marijns95@gmail.com,
martin.botka1@gmail.com, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register
Date: Mon, 28 Sep 2020 10:21:08 -0600 [thread overview]
Message-ID: <20200928162107.GC29832@jcrouse1-lnx.qualcomm.com> (raw)
In-Reply-To: <20200926125146.12859-2-kholk11@gmail.com>
On Sat, Sep 26, 2020 at 02:51:40PM +0200, kholk11@gmail.com wrote:
> From: AngeloGioacchino Del Regno <kholk11@gmail.com>
>
> The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
> programmed to some different values on a per-model basis.
> At least, this is what we intend to do here;
>
> Unfortunately, though, this register is being overwritten with a
> static magic number, right after applying the GPU-specific
> configuration (including the GPU-specific quirks) and that is
> effectively nullifying the efforts.
>
> Let's remove the redundant and wrong write to the PC_DBG_ECO_CNTL
> register in order to retain the wanted configuration for the
> target GPU.
This was probably inherited from downstream which doesn't mind RMWing the same
register multiple times.
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
> Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 91726da82ed6..6262603e6e2e 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -594,8 +594,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
> if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
> gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
>
> - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100);
> -
> /* Enable USE_RETENTION_FLOPS */
> gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);
>
> --
> 2.28.0
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-09-28 16:21 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-26 12:51 [PATCH 0/7] Add support for Adreno 508/509/512 kholk11
2020-09-26 12:51 ` [PATCH 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register kholk11
2020-09-28 16:21 ` Jordan Crouse [this message]
2020-09-26 12:51 ` [PATCH 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch kholk11
2020-09-28 16:22 ` Jordan Crouse
2020-09-26 12:51 ` [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs kholk11
2020-09-26 13:33 ` Martin Botka
2020-09-28 16:24 ` Jordan Crouse
2020-09-26 12:51 ` [PATCH 4/7] drm/msm/a5xx: Reset VBIF before PC only on A510 and A530 kholk11
2020-09-28 16:25 ` Jordan Crouse
2020-09-26 12:51 ` [PATCH 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write() kholk11
2020-09-28 16:15 ` Jordan Crouse
2020-09-28 20:29 ` AngeloGioacchino Del Regno
2020-09-26 12:51 ` [PATCH 6/7] drm/msm/a5xx: Disable flat shading optimization kholk11
2020-09-27 18:56 ` Rob Clark
2020-09-26 12:51 ` [PATCH 7/7] drm/msm/a5xx: Disable UCHE global filter kholk11
2020-09-27 18:51 ` Rob Clark
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