From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6701BC55ABD for ; Tue, 10 Nov 2020 18:46:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15A0820797 for ; Tue, 10 Nov 2020 18:46:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="r5fnNgvL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731440AbgKJSq5 (ORCPT ); Tue, 10 Nov 2020 13:46:57 -0500 Received: from m42-4.mailgun.net ([69.72.42.4]:25940 "EHLO m42-4.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731315AbgKJSq5 (ORCPT ); Tue, 10 Nov 2020 13:46:57 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1605034017; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=IZO6rnh8ZWoFV5rz+v+qH/+fcVcTytNYpXi3s4eL7GM=; b=r5fnNgvL+nPC+Mquk1EybSpQaySfzR8m3AUkX8JfSQG+ud224FzXwMYmTUNatyT0BHVN8/KS hvZFlljL9rbpCgS/3F2ENiagA1qkIEtRNzl79kruH1QkXBrhqoOy5Fi4WKu9sFTwrrJqbYnT Azjgy1D1zuNQTDPJ7GP4mXmvN3A= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-west-2.postgun.com with SMTP id 5faadff1e9dd187f53413ff0 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 10 Nov 2020 18:46:09 GMT Sender: jcrouse=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id CC7E2C43387; Tue, 10 Nov 2020 18:46:09 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id C00BEC433C6; Tue, 10 Nov 2020 18:46:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C00BEC433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=jcrouse@codeaurora.org Date: Tue, 10 Nov 2020 11:46:04 -0700 From: Jordan Crouse To: Rob Clark Cc: dri-devel@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jonathan Marek , Sharat Masetty , Eric Anholt , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list Subject: Re: [PATCH 1/2] drm/msm/a6xx: Clear shadow on suspend Message-ID: <20201110184604.GA2661@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , dri-devel@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jonathan Marek , Sharat Masetty , Eric Anholt , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20201110184401.282982-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201110184401.282982-1-robdclark@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Nov 10, 2020 at 10:43:59AM -0800, Rob Clark wrote: > From: Rob Clark > > Clear the shadow rptr on suspend. Otherwise, when we resume, we can > have a stale value until CP_WHERE_AM_I executes. If we suspend near > the ringbuffer wraparound point, this can lead to a chicken/egg > situation where we are waiting for ringbuffer space to write the > CP_WHERE_AM_I (or CP_INIT) packet, because we mistakenly believe that > the ringbuffer is full (due to stale rptr value in the shadow). > > Fixes errors like: > > [drm:adreno_wait_ring [msm]] *ERROR* timeout waiting for space in ringbuffer 0 > > in the resume path. > > Fixes: d3a569fccfa0 ("drm/msm: a6xx: Use WHERE_AM_I for eligible targets") > Signed-off-by: Rob Clark Reviewed-by: Jordan Crouse > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 2f236aadfa9c..fcb0aabbc985 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1043,12 +1043,21 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + int i, ret; > > trace_msm_gpu_suspend(0); > > devfreq_suspend_device(gpu->devfreq.devfreq); > > - return a6xx_gmu_stop(a6xx_gpu); > + ret = a6xx_gmu_stop(a6xx_gpu); > + if (ret) > + return ret; > + > + if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) > + for (i = 0; i < gpu->nr_rings; i++) > + a6xx_gpu->shadow[i] = 0; > + > + return 0; > } > > static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) > -- > 2.28.0 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project