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* [PATCH v1] i2c: qcom: Fix IRQ error misassignement
@ 2020-11-26 14:53 Robert Foss
  2020-11-26 15:03 ` Manivannan Sadhasivam
  0 siblings, 1 reply; 4+ messages in thread
From: Robert Foss @ 2020-11-26 14:53 UTC (permalink / raw)
  To: loic.poulain, robert.foss, linux-i2c, linux-arm-msm, linux-kernel

During cci_isr() errors read from register fields belonging to
i2c master1 are currently assigned to the status field belonging to
i2c master0. This patch corrects this error, and always assigns
master1 errors to the status field of master1.

Suggested-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
 drivers/i2c/busses/i2c-qcom-cci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c
index f13735beca58..1c259b5188de 100644
--- a/drivers/i2c/busses/i2c-qcom-cci.c
+++ b/drivers/i2c/busses/i2c-qcom-cci.c
@@ -194,9 +194,9 @@ static irqreturn_t cci_isr(int irq, void *dev)
 	if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) {
 		if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR ||
 			val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR)
-			cci->master[0].status = -ENXIO;
+			cci->master[1].status = -ENXIO;
 		else
-			cci->master[0].status = -EIO;
+			cci->master[1].status = -EIO;
 
 		writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
 		ret = IRQ_HANDLED;
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2020-11-26 16:10 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2020-11-26 14:53 [PATCH v1] i2c: qcom: Fix IRQ error misassignement Robert Foss
2020-11-26 15:03 ` Manivannan Sadhasivam
2020-11-26 15:58   ` Robert Foss
2020-11-26 16:10     ` Manivannan Sadhasivam

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