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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id b12sm3845680oti.17.2021.04.13.19.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 19:47:14 -0700 (PDT) Date: Tue, 13 Apr 2021 21:47:12 -0500 From: Bjorn Andersson To: Manivannan Sadhasivam List-Id: Cc: soc@kernel.org, linux@armlinux.org.uk, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v3] ARM: kernel: Fix interrupted SMC calls Message-ID: <20210414024712.GX1538589@yoga> References: <20210326182237.47048-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210326182237.47048-1-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 26 Mar 13:22 CDT 2021, Manivannan Sadhasivam wrote: > On Qualcomm ARM32 platforms, the SMC call can return before it has > completed. If this occurs, the call can be restarted, but it requires > using the returned session ID value from the interrupted SMC call. > > The ARM32 SMCC code already has the provision to add platform specific > quirks for things like this. So let's make use of it and add the > Qualcomm specific quirk (ARM_SMCCC_QUIRK_QCOM_A6) used by the QCOM_SCM > driver. > > This change is similar to the below one added for ARM64 a while ago: > commit 82bcd087029f ("firmware: qcom: scm: Fix interrupted SCM calls") > > Without this change, the Qualcomm ARM32 platforms like SDX55 will return > -EINVAL for SMC calls used for modem firmware loading and validation. > > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > > Changes in v3: > > * Rebased on top of v5.12-rc2 > * Sent to SoC list since there was no review so far apart from initial one > by Russel > > Changes in v2: > > * Preserved callee saved registers and used the registers r4, r5 which > are getting pushed onto the stack. > > arch/arm/kernel/asm-offsets.c | 3 +++ > arch/arm/kernel/smccc-call.S | 11 ++++++++++- > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c > index be8050b0c3df..70993af22d80 100644 > --- a/arch/arm/kernel/asm-offsets.c > +++ b/arch/arm/kernel/asm-offsets.c > @@ -24,6 +24,7 @@ > #include > #include > #include > +#include > #include "signal.h" > > /* > @@ -148,6 +149,8 @@ int main(void) > DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys)); > DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash)); > #endif > + DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); > + DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); > BLANK(); > DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); > DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); > diff --git a/arch/arm/kernel/smccc-call.S b/arch/arm/kernel/smccc-call.S > index 00664c78faca..931df62a7831 100644 > --- a/arch/arm/kernel/smccc-call.S > +++ b/arch/arm/kernel/smccc-call.S > @@ -3,7 +3,9 @@ > * Copyright (c) 2015, Linaro Limited > */ > #include > +#include > > +#include > #include > #include > #include > @@ -27,7 +29,14 @@ UNWIND( .fnstart) > UNWIND( .save {r4-r7}) > ldm r12, {r4-r7} > \instr > - pop {r4-r7} > + ldr r4, [sp, #36] > + cmp r4, #0 > + beq 1f // No quirk structure > + ldr r5, [r4, #ARM_SMCCC_QUIRK_ID_OFFS] > + cmp r5, #ARM_SMCCC_QUIRK_QCOM_A6 > + bne 1f // No quirk present > + str r6, [r4, #ARM_SMCCC_QUIRK_STATE_OFFS] > +1: pop {r4-r7} > ldr r12, [sp, #(4 * 4)] > stm r12, {r0-r3} > bx lr > -- > 2.25.1 >