[PATCH 03/11] clk: qcom: camcc-sc7180: get rid of the test clock

Dmitry Baryshkov
2021-12-08T17:54:39Z

The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/camcc-sc7180.c | 65 +++++++++++++--------------------
1 file changed, 25 insertions(+), 40 deletions(-)

diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
index ce73ee9037cb..3c15e551419f 100644
--- a/drivers/clk/qcom/camcc-sc7180.c
+++ b/drivers/clk/qcom/camcc-sc7180.c
@@ -29,7 +29,6 @@ enum {
P_CAM_CC_PLL2_OUT_AUX,
P_CAM_CC_PLL2_OUT_EARLY,
P_CAM_CC_PLL3_OUT_MAIN,
- P_CORE_BI_PLL_TEST_SE,
};

static const struct pll_vco agera_vco[] = {
@@ -187,26 +186,22 @@ static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll1.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_AUX, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll2_out_aux.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct parent_map cam_cc_parent_map_2[] = {
@@ -214,7 +209,6 @@ static const struct parent_map cam_cc_parent_map_2[] = {
{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_2[] = {
@@ -222,7 +216,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .hw = &cam_cc_pll2_out_early.hw },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct parent_map cam_cc_parent_map_3[] = {
@@ -231,7 +224,6 @@ static const struct parent_map cam_cc_parent_map_3[] = {
{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_3[] = {
@@ -240,33 +232,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .hw = &cam_cc_pll2_out_early.hw },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct parent_map cam_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll0.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct parent_map cam_cc_parent_map_6[] = {
@@ -274,7 +261,6 @@ static const struct parent_map cam_cc_parent_map_6[] = {
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};

static const struct clk_parent_data cam_cc_parent_data_6[] = {
@@ -282,7 +268,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .hw = &cam_cc_pll1.clkr.hw },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};

static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
@@ -303,7 +288,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_2,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -324,7 +309,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_5,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -338,7 +323,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_5,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -359,7 +344,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_3,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -378,7 +363,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -392,7 +377,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -406,7 +391,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -420,7 +405,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -442,7 +427,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -465,7 +450,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_2,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -487,7 +472,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_4,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -509,7 +494,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_data = cam_cc_parent_data_3,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -523,7 +508,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_4,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -537,7 +522,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_data = cam_cc_parent_data_3,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -551,7 +536,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_4,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -566,7 +551,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_3,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -589,7 +574,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_data = cam_cc_parent_data_2,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -612,7 +597,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_2,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -634,7 +619,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src",
.parent_data = cam_cc_parent_data_6,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -655,7 +640,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -669,7 +654,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -683,7 +668,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -697,7 +682,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -711,7 +696,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -730,7 +715,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
--
2.33.0