From: Stephen Boyd <sboyd@kernel.org>
To: Rohit Agarwal <quic_rohiagar@quicinc.com>,
agross@kernel.org, bjorn.andersson@linaro.org,
manivannan.sadhasivam@linaro.org, mturquette@baylibre.com
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
Rohit Agarwal <quic_rohiagar@quicinc.com>
Subject: Re: [PATCH v2 4/7] clk: qcom: Add A7 PLL support for SDX65
Date: Thu, 17 Feb 2022 16:22:55 -0800 [thread overview]
Message-ID: <20220218002257.018E4C340E8@smtp.kernel.org> (raw)
In-Reply-To: <1644919338-27393-1-git-send-email-quic_rohiagar@quicinc.com>
Quoting Rohit Agarwal (2022-02-15 02:02:18)
> Add support for PLL found in Qualcomm SDX65 platforms which is used to
> provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
> frequency clock to the CPU above 1GHz as compared to the other sources
> like GPLL0.
>
> In this driver, the power domain is attached to the cpudev. This is
> required for CPUFreq functionality and there seems to be no better place
> to do other than this driver (no dedicated CPUFreq driver).
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
prev parent reply other threads:[~2022-02-18 0:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-15 10:02 [PATCH v2 4/7] clk: qcom: Add A7 PLL support for SDX65 Rohit Agarwal
2022-02-18 0:22 ` Stephen Boyd [this message]
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