From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF548C433EF for ; Mon, 2 May 2022 21:58:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378311AbiEBWBh (ORCPT ); Mon, 2 May 2022 18:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387789AbiEBV7w (ORCPT ); Mon, 2 May 2022 17:59:52 -0400 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [5.144.164.169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FB5D63E2 for ; Mon, 2 May 2022 14:56:19 -0700 (PDT) Received: from SoMainline.org (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 607113F549; Mon, 2 May 2022 23:56:17 +0200 (CEST) Date: Mon, 2 May 2022 23:56:16 +0200 From: Marijn Suijten To: Dmitry Baryshkov Cc: Abhinav Kumar , freedreno@lists.freedesktop.org, kernel test robot , David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , Rob Clark , Daniel Vetter , Bjorn Andersson , Sean Paul Subject: Re: [Freedreno] [PATCH v2] drm/msm/dsi: use RMW cycles in dsi_update_dsc_timing Message-ID: <20220502215616.jwpi3dr6ryembsfr@SoMainline.org> References: <20220430175533.3817792-1-dmitry.baryshkov@linaro.org> <20220430185807.yn2j2coyc77qzx2o@SoMainline.org> <20220501200635.ekl3fw47dv2zytt3@SoMainline.org> <20220502083442.t365cfmivlga557g@SoMainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2022-05-02 13:02:09, Dmitry Baryshkov wrote: > [snip] > > How would you represent this in XML? I was hoping for a method that > > allows to construct the value in a generic way, without register names, > > and then simply have a "register macro" that moves (and perhaps masks) > > the preconstructed value into the right place. A bit like how `enum`s > > are currently set up in XML, but with bit ranges for the values and > > macros to set a value. > > > > I think I've _partially_ found what I was looking for: a ``. > > However, I don't know if we can utilize this multiple times within a > > single `reg32`, once with an offset for stream1. Alas, it's just > > bikeshedding at this point. > > Unfortunately the following naïve patch doesn't work, stream1 bits are > still defined in the 0:15 bit space. One would have to modify rnn tool > to make sure that it takes into account the low/high parts of the > bitfield when generating offsets/masks. > > diff --git a/src/freedreno/registers/dsi/dsi.xml > b/src/freedreno/registers/dsi/dsi.xml > index f2eef4ff41ae..b0166628ad0a 100644 > --- a/src/freedreno/registers/dsi/dsi.xml > +++ b/src/freedreno/registers/dsi/dsi.xml > @@ -361,22 +361,19 @@ > xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> > > > > - > - > + > > type="uint"/> > type="uint"/> > > + > + > + > + type="COMPRESSION_MODE_CTRL"/> > > > - type="uint"/> > - type="uint"/> > - type="uint"/> > - > - type="uint"/> > - type="uint"/> > - type="uint"/> > - > + type="COMPRESSION_MODE_CTRL"/> > + type="COMPRESSION_MODE_CTRL"/> > > > type="uint"/> This is approximately what I was aiming for. `inline="true"` does "inline" all the individual bitfields so that they're prefixed with the reg32+bitfield name again, right? That's what I wanted to avoid :) - Marijn