From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4B07C43334 for ; Wed, 8 Jun 2022 10:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237120AbiFHKwu (ORCPT ); Wed, 8 Jun 2022 06:52:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236995AbiFHKwq (ORCPT ); Wed, 8 Jun 2022 06:52:46 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D6531EE6EB for ; Wed, 8 Jun 2022 03:52:44 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id a29so4102170lfk.2 for ; Wed, 08 Jun 2022 03:52:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mXAgxvBD8Vm/kAFiyUCWCOJ/VNmh68M1AKZjIPsv5N4=; b=hLiJ1PI4R28gJYM3IJdzjR0/gNzu3ZIOXBd3H0sccRPtec5NgGosB4YoILdf3ubAto e6E5m7E1uPo01nCJN2PBL1NcAXCTwZI4QrbwSBgJOpzkZLkpq8PvoimHZyTLk00kbZmU PgvoBshUOFa08gt/TyShVB4tT/ZyCzMUoBeOS10p9uymKgEVIwkN0Su/7OUpIjlU+18r 43NjieQcYjrTo8fvSXyMiDF7Uzoy/NPk4ADI2Y3E07yjbszqx49iH6NeMol5Lv+5bfDY Dr4UTf3QLsZQ6/pUuZwQW/h4rSe9+rKi/Lgk3OWI9Rp1zzB7WgLs/5mjMCfFKsGr7vOO W9QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mXAgxvBD8Vm/kAFiyUCWCOJ/VNmh68M1AKZjIPsv5N4=; b=lL57FSezKbmLwnk4M6WK9h/moiQNQOjkUXkGXbKBu8Lpjawh8PKH5E1EFV2RJuQnWt CNUE+vXp39OHX60AvysPDqVR5pDwXuYZBju27/9EmcR95wkmwuupa66i0JPuc3exyl28 2+gxGrhMfYPa0DoOr1gkEP7FohQ/7/uA/0oGlVlxBPiQMu5fUFTKD0fLg5ve0zIbv5mz YE9ie4bIjPcb7G3bAs1kRpaXPlcCdV5nS4/oyIU61auZmUajTeuWyMbZYALHDABs5FCT 9suvkDat2YWyn91+2SlBgncLbYpheMvGs8F9FKv4TjgVIaE8YI8WyJGiUXa+68907zO2 F6ww== X-Gm-Message-State: AOAM533V15kC7y3LVUADPtcTz6nuUdIdhXkKQix3dUHT/PnHY+RI5Vk3 lhWXXogT7MMH2RxXr47qPwkfpA== X-Google-Smtp-Source: ABdhPJyrAtmrOqIhZhQz0VNyBYBQFnPN8D7xVx3+Ngbuwn5gsHxOhMSGmTw/aph++fHMW9IX1pg8aw== X-Received: by 2002:a05:6512:16aa:b0:479:7df:cb68 with SMTP id bu42-20020a05651216aa00b0047907dfcb68mr14721609lfb.666.1654685562393; Wed, 08 Jun 2022 03:52:42 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e9-20020a2e5009000000b002556b0cd5acsm3232337ljb.56.2022.06.08.03.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:52:41 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH v11 3/5] clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks Date: Wed, 8 Jun 2022 13:52:36 +0300 Message-Id: <20220608105238.2973600-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608105238.2973600-1-dmitry.baryshkov@linaro.org> References: <20220608105238.2973600-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sc7280.c | 49 +++++++++++------------------------ 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 423627d49719..7ff64d4d5920 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -17,6 +17,7 @@ #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "common.h" #include "gdsc.h" #include "reset.h" @@ -255,26 +256,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .hw = &gcc_gpll0_out_even.clkr.hw }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -369,32 +350,32 @@ static const struct clk_parent_data gcc_parent_data_15[] = { { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x6b054, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + .name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x8d054, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + .name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -- 2.35.1