From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
Johan Hovold <johan@kernel.org>
Subject: [RFC PATCH 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header
Date: Fri, 10 Jun 2022 22:09:09 +0300 [thread overview]
Message-ID: <20220610190925.3670081-13-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220610190925.3670081-1-dmitry.baryshkov@linaro.org>
Move QSERDES PLL registers to the separate header. This register set is
unique for the IPQ PCIe Gen3 PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 66 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 58 +---------------
2 files changed, 67 insertions(+), 57 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
new file mode 100644
index 000000000000..ad326e301a3a
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_
+#define QCOM_PHY_QMP_QSERDES_PLL_H_
+
+/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
+#define QSERDES_PLL_BG_TIMER 0x00c
+#define QSERDES_PLL_SSC_PER1 0x01c
+#define QSERDES_PLL_SSC_PER2 0x020
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
+#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
+#define QSERDES_PLL_CLK_ENABLE1 0x040
+#define QSERDES_PLL_SYS_CLK_CTRL 0x044
+#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
+#define QSERDES_PLL_PLL_IVCO 0x050
+#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
+#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
+#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
+#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
+#define QSERDES_PLL_BG_TRIM 0x074
+#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
+#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
+#define QSERDES_PLL_CP_CTRL_MODE0 0x080
+#define QSERDES_PLL_CP_CTRL_MODE1 0x084
+#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
+#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
+#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
+#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
+#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
+#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
+#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
+#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
+#define QSERDES_PLL_DEC_START_MODE0 0x0cc
+#define QSERDES_PLL_DEC_START_MODE1 0x0d0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
+#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
+#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
+#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
+#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
+#define QSERDES_PLL_VCO_TUNE_MAP 0x120
+#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
+#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
+#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
+#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
+#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
+#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
+#define QSERDES_PLL_CLK_SELECT 0x16c
+#define QSERDES_PLL_HSCLK_SEL 0x170
+#define QSERDES_PLL_CORECLK_DIV 0x17c
+#define QSERDES_PLL_CORE_CLK_EN 0x184
+#define QSERDES_PLL_CMN_CONFIG 0x18c
+#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
+#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 50a663bb0f2f..07e281c818b1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -18,63 +18,7 @@
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
-
-#define QSERDES_PLL_BG_TIMER 0x00c
-#define QSERDES_PLL_SSC_PER1 0x01c
-#define QSERDES_PLL_SSC_PER2 0x020
-#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
-#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
-#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
-#define QSERDES_PLL_CLK_ENABLE1 0x040
-#define QSERDES_PLL_SYS_CLK_CTRL 0x044
-#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
-#define QSERDES_PLL_PLL_IVCO 0x050
-#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
-#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
-#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
-#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
-#define QSERDES_PLL_BG_TRIM 0x074
-#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
-#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
-#define QSERDES_PLL_CP_CTRL_MODE0 0x080
-#define QSERDES_PLL_CP_CTRL_MODE1 0x084
-#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
-#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
-#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
-#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
-#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
-#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
-#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
-#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
-#define QSERDES_PLL_DEC_START_MODE0 0x0cc
-#define QSERDES_PLL_DEC_START_MODE1 0x0d0
-#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
-#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
-#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
-#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
-#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
-#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
-#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
-#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
-#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
-#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
-#define QSERDES_PLL_VCO_TUNE_MAP 0x120
-#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
-#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
-#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
-#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
-#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
-#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
-#define QSERDES_PLL_CLK_SELECT 0x16c
-#define QSERDES_PLL_HSCLK_SEL 0x170
-#define QSERDES_PLL_CORECLK_DIV 0x17c
-#define QSERDES_PLL_CORE_CLK_EN 0x184
-#define QSERDES_PLL_CMN_CONFIG 0x18c
-#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
-#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+#include "phy-qcom-qmp-qserdes-pll.h"
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
--
2.35.1
next prev parent reply other threads:[~2022-06-10 19:09 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 19:08 [RFC PATCH 00/28] phy: qcom-qmp: split register tables Dmitry Baryshkov
2022-06-10 19:08 ` [RFC PATCH 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register Dmitry Baryshkov
2022-06-10 19:08 ` [RFC PATCH 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3 Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 06/28] phy: qcom-qmp: rename QMP V2 PCS registers Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3 Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 08/28] phy: qcom-qmp: move QSERDES registers to separate header Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 10/28] phy: qcom-qmp: move QSERDES V4 " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 11/28] phy: qcom-qmp: move QSERDES V5 " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov [this message]
2022-06-10 19:09 ` [RFC PATCH 13/28] phy: qcom-qmp: move PCS V2 registers to separate header Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 15/28] phy: qcom-qmp: move PCS V4 " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 21/28] phy: qcom-qmp: qserdes-com: add missing registers Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 22/28] phy: qcom-qmp: qserdes-com-v3: " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 23/28] phy: qcom-qmp: qserdes-com-v4: " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 24/28] phy: qcom-qmp: qserdes-com-v5: " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 25/28] phy: qcom-qmp: pcs-v3: " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 26/28] phy: qcom-qmp: pcs-pcie-v4: " Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996 Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Dmitry Baryshkov
2022-07-05 7:05 ` [RFC PATCH 00/28] phy: qcom-qmp: split register tables Vinod Koul
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