[PATCH v6 05/12] dt-bindings: display/msm: move common MDSS properties to mdss-common.yaml

Dmitry Baryshkov
2022-09-01T10:23:26Z

Move properties common to all MDSS DT nodes to the mdss-common.yaml.

This extends qcom,msm8998-mdss schema to allow interconnect nodes, which
will be added later, once msm8998 gains interconnect support.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/display/msm/dpu-msm8998.yaml | 42 ++--------
.../bindings/display/msm/dpu-qcm2290.yaml | 52 ++----------
.../bindings/display/msm/dpu-sc7180.yaml | 51 ++----------
.../bindings/display/msm/dpu-sc7280.yaml | 51 ++----------
.../bindings/display/msm/dpu-sdm845.yaml | 55 ++----------
.../bindings/display/msm/mdss-common.yaml | 83 +++++++++++++++++++
6 files changed, 116 insertions(+), 218 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-common.yaml

diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
index 0d6743eabd27..1e6b7e15f1c5 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml
@@ -14,20 +14,14 @@ description: |
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for MSM8998 target.

+allOf:
+ - $ref: /schemas/display/msm/mdss-common.yaml#
+
properties:
compatible:
items:
- const: qcom,msm8998-mdss

- reg:
- maxItems: 1
-
- reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
-
clocks:
items:
- description: Display AHB clock
@@ -40,23 +34,8 @@ properties:
- const: bus
- const: core

- interrupts:
- maxItems: 1
-
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-
- ranges: true
+ maxItems: 1

patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -102,18 +81,7 @@ patternProperties:
- const: core
- const: vsync

-required:
- - compatible
- - reg
- - reg-names
- - power-domains
- - clocks
- - interrupts
- - interrupt-controller
- - iommus
- - ranges
-
-additionalProperties: false
+unevaluatedProperties: false

examples:
- |
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
index bec3c131c0dc..1c6dd7969a61 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml
@@ -14,20 +14,14 @@ description: |
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
and DPU are mentioned for QCM2290 target.

+allOf:
+ - $ref: /schemas/display/msm/mdss-common.yaml#
+
properties:
compatible:
items:
- const: qcom,qcm2290-mdss

- reg:
- maxItems: 1
-
- reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
-
clocks:
items:
- description: Display AHB clock from gcc
@@ -40,35 +34,14 @@ properties:
- const: bus
- const: core

- interrupts:
- maxItems: 1
-
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
-
- ranges: true
+ maxItems: 2

interconnects:
- items:
- - description: Interconnect path specifying the port ids for data bus
+ maxItems: 1

interconnect-names:
- const: mdp0-mem
-
- resets:
- items:
- - description: MDSS_CORE reset
+ maxItems: 1

patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -110,18 +83,7 @@ patternProperties:
- const: lut
- const: vsync

-required:
- - compatible
- - reg
- - reg-names
- - power-domains
- - clocks
- - interrupts
- - interrupt-controller
- - iommus
- - ranges
-
-additionalProperties: false
+unevaluatedProperties: false

examples:
- |
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
index 732b9d8f968a..47e74f78e939 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
@@ -14,20 +14,14 @@ description: |
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SC7180 target.

+allOf:
+ - $ref: /schemas/display/msm/mdss-common.yaml#
+
properties:
compatible:
items:
- const: qcom,sc7180-mdss

- reg:
- maxItems: 1
-
- reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
-
clocks:
items:
- description: Display AHB clock from gcc
@@ -40,34 +34,14 @@ properties:
- const: ahb
- const: core

- interrupts:
- maxItems: 1
-
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-
- ranges: true
+ maxItems: 1

interconnects:
- items:
- - description: Interconnect path specifying the port ids for data bus
+ maxItems: 1

interconnect-names:
- const: mdp0-mem
-
- resets:
- items:
- - description: MDSS_CORE reset
+ maxItems: 1

patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -111,18 +85,7 @@ patternProperties:
- const: core
- const: vsync

-required:
- - compatible
- - reg
- - reg-names
- - power-domains
- - clocks
- - interrupts
- - interrupt-controller
- - iommus
- - ranges
-
-additionalProperties: false
+unevaluatedProperties: false

examples:
- |
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
index 4889129660c6..7dc624a26e2e 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
@@ -14,19 +14,13 @@ description: |
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SC7280.

+allOf:
+ - $ref: /schemas/display/msm/mdss-common.yaml#
+
properties:
compatible:
const: qcom,sc7280-mdss

- reg:
- maxItems: 1
-
- reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
-
clocks:
items:
- description: Display AHB clock from gcc
@@ -39,34 +33,14 @@ properties:
- const: ahb
- const: core

- interrupts:
- maxItems: 1
-
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-
- ranges: true
+ maxItems: 1

interconnects:
- items:
- - description: Interconnect path specifying the port ids for data bus
+ maxItems: 1

interconnect-names:
- const: mdp0-mem
-
- resets:
- items:
- - description: MDSS_CORE reset
+ maxItems: 1

patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -109,18 +83,7 @@ patternProperties:
- const: core
- const: vsync

-required:
- - compatible
- - reg
- - reg-names
- - power-domains
- - clocks
- - interrupts
- - interrupt-controller
- - iommus
- - ranges
-
-additionalProperties: false
+unevaluatedProperties: false

examples:
- |
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
index b275f928a921..7e9d7c7f3538 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -14,20 +14,14 @@ description: |
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SDM845 target.

+allOf:
+ - $ref: /schemas/display/msm/mdss-common.yaml#
+
properties:
compatible:
items:
- const: qcom,sdm845-mdss

- reg:
- maxItems: 1
-
- reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
-
clocks:
items:
- description: Display AHB clock from gcc
@@ -38,38 +32,14 @@ properties:
- const: iface
- const: core

- interrupts:
- maxItems: 1
-
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
-
- ranges: true
+ maxItems: 2

interconnects:
- items:
- - description: Interconnect path specifying the port ids for data bus
- - description: Interconnect path specifying the port ids for data bus
+ maxItems: 2

interconnect-names:
- items:
- - const: mdp0-mem
- - const: mdp1-mem
-
- resets:
- items:
- - description: MDSS_CORE reset
+ maxItems: 2

patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -111,18 +81,7 @@ patternProperties:
- const: core
- const: vsync

-required:
- - compatible
- - reg
- - reg-names
- - power-domains
- - clocks
- - interrupts
- - interrupt-controller
- - iommus
- - ranges
-
-additionalProperties: false
+unevaluatedProperties: false

examples:
- |
diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
new file mode 100644
index 000000000000..053c1e889552
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display MDSS dt properties (common properties)
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+ - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+ - Rob Clark <robdclark@gmail.com>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc.
+
+properties:
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ minItems: 1
+ items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
+
+ ranges: true
+
+ interconnects:
+ minItems: 1
+ items:
+ - description: Interconnect path specifying the port ids for data bus
+ - description: Interconnect path specifying the port ids for data bus
+
+ interconnect-names:
+ minItems: 1
+ items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+
+ resets:
+ items:
+ - description: MDSS_CORE reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ranges
+
+additionalProperties: true
--
2.35.1